PM7312 pmc-sierra, PM7312 Datasheet - Page 260

• Manufacturer Part Number: PM7312
• Description: Freedm 32a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021833, Issue 2
14.6 Transmit APPI Timing (Any-PHY Level 3)
asserted 2 cycles after the RSX allowing the controller to identify the start of packet. The first two
bytes indicate the Any-PHY channel (CH 2) while the next two bytes contain either a connection
identifier or the first two bytes of the packet.
During the cycle when D2 is placed on RXDATA[7:0], the external controller is unable to accept
any further data and sets RENB high. Two RXCLK cycles later, the FREEDM 32A1024L pauses
the Rx APPI. The external controller may hold RENB high for an indeterminate number of
RXCLK cycles. The FREEDM 32A1024L will wait until the external controller returns RENB
low.
The FREEDM 32A1024L will not pause burst data transfers across the Rx APPI.
The RVAL and REOP signals indicate the presence and end of valid packet data respectively. The
RERR and RMOD signals are only valid at the end of a packet and are qualified with the REOP
signal. When a packet is erred, the FREEDM 32A1024L may be programmed to overwrite
RXDATA[7:0] in the final word of packet transfer with status information indicating the cause of
the error. RXDATA[7:0] is not modified if a packet is error free
The transmit Any-PHY packet interface (APPI) timing is shown in Figure 47 through Figure 49. An
external controller provides data to the FREEDM 32A1024L device using the transmit APPI. The
following discussion surrounding the transmit APPI functional timing assumes that point to point
interfaces exist between FREEDM 32A1024L and the external controller. The FREEDM 32A1024L
compares the TXADDR[15:0] to the base and range address registers to determine if the address is
destined for the FREEDM 32A1024L.
Figure 47 Transmit APPI Timing Any-PHY Level 3 (Normal Transfer)
Figure 47 shows transfer of a 254 byte packet on the Tx APPI of FREEDM 32A1024L. The start of
all burst data transfers is qualified with the TSX signal and an in-band Any-PHY channel address
on TXDATA[7:0] to associate the data to follow with an Any-PHY channel. The TEOP signal
indicates the end of valid packet data. The TERR signal is held low except at the end of a packet
(TEOP set high).
The TRDY signal is valid one TXCLK cycle after TSX is sampled high. Upon sampling the TRDY
signal high, the external controller completes the current burst data transfer. This is the case for the
TXDATA[7:0]
TXPRTY
TXCLK
TRDY
TEOP
TERR
TSX
CH 0 CH 0 CI 1
CI 2
FREEDM 32A1024L ASSP Telecom Standard Product Data Sheet
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11 D252 D253
Released
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