MT90500 Mitel Semiconductor, MT90500 Datasheet
MT90500
Manufacturer Part Number
MT90500
Description
Multi-Channel ATM AAL1 SAR
Manufacturer
Mitel Semiconductor
Datasheet
1.MT90500.pdf
(159 pages)
Available stocks
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Part Number
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Quantity
Price
Company:
Part Number:
MT90500AL
Manufacturer:
HITACHI
Quantity:
5 510
Part Number:
MT90500AL
Manufacturer:
MITEL
Quantity:
20 000
Features
•
•
•
•
•
•
•
•
•
From
External
ATM SAR
To/From
External
PHY
AAL1 Segmentation and Reassembly device
compatible with Structured Data Transfer (SDT)
as per ANSI T1.630 and ITU I.363 standards
Transports 64kbps and N x 64kbps traffic over
ATM AAL1 cells (also over AAL5 or AAL0)
Simultaneous processing of up to 1024
bidirectional Virtual Circuits
Flexible aggregation capabilities (Nx64) to
allow any combination of 64 kbps channels
while maintaining frame integrity (DS0
grooming)
Support for clock recovery - Adaptive Clock
Recovery, Synchronous Residual Time Stamp
(SRTS), or external
Primary UTOPIA port (Level 1, 25 MHz) for
connection to external PHY devices with data
throughput of up to 155 Mbps
Secondary UTOPIA port for connection to an
external AAL5 SAR processor, or for chaining
multiple MT90500 devices
16-bit microprocessor port, configurable to
Motorola or Intel timing
TDM bus provides 16 bidirectional serial TDM
Main
UTOPIA
Interface
Secondary
UTOPIA
Interface
UTOPIA Module
UTOPIA
UTOPIA
RX
MUX
TX
Figure A - MT90500 Block Diagram
Lookup
Tables
VC
Boundary Scan
External Memory Controller
Interface
AAL1
AAL1
JTAG
SAR
SAR
TX
RX
and Circular Buffers
Control Structures
DS5171
•
•
•
•
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•
TX / RX
streams at 2.048, 4.096, or 8.192 Mbps for up
to 2048 TDM 64 kbps channels
Compatible with ST-BUS, MVIP, H-MVIP and
SCSA interfaces
Supports master and slave TDM bus clock
operation
Loopback function at TDM bus interface
Local TDM bus provides clocks, input pin and
output pin for 2.048 Mbps operation
Master clock rate up to 60 MHz
Dual rails (3.3V for power minimization, 5V for
standard I/O)
IEEE1149 (JTAG) interface
Internal
MT90500AL
Frame
Buffer
TDM
Multi-Channel ATM AAL1 SAR
16-bit Microprocessor Address
Microprocessor
and Data Buses
Ordering Information
Registers
Interface
External
Synchronous
SRAM
TDM Module
-40 to +85 C
TDM Bus
Recovery
Interface
TDM
Clock
Logic
Clock
240 Pin Plastic QFP
ISSUE 4
MT90500
TDM Bus
16 Lines
2048 x 64 kbps
(max.)
Local TDM Bus
32 x 64 kbps in
32 x 64 kbps out
Clock Signals
April 1999
1
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