MT90500 Mitel Semiconductor, MT90500 Datasheet - Page 24

• Manufacturer Part Number: MT90500
• Description: Multi-Channel ATM AAL1 SAR
• Manufacturer: Mitel Semiconductor

MT90500
24
CORSIGC / MCTX /
CORSIGD / MCRX /
MEM_CS[1:0][H:L]
MEM_ADD[17:0]
CORSIGB / MC /
MEM_DAT[31:0]
MEM_PAR[3:0]
PTXDATA[7:0]
MEM_WR[3:0]
RDY/DTACK
SRTSDATA
REF8KCLK
CORSIGA/
SRTSENA
FREERUN
Pin Name
STXCLAV
CORSIGE
MEMCLK
MEM_OE
PTXSOC
PTXPAR
CLKFAIL
/ MCCLK
PTXCLK
ST[15:0]
PTXEN
FSYNC
D[15:0]
SEC8K
CLKx1
LOCx2
LOCx1
FNXI
TDO
INT
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Active during and after reset.
Active during and after reset.
High-impedance
Active during and after reset.
Active during and after reset.
Active during and after reset.
Continues to drive at MCLK
rate during reset.
Active during and after reset.
Active during and after reset.
Active HIGH during reset.
Active during and after reset.
High-impedance
High-impedance
Active during and after reset.
Tristated when CS is HIGH.
High-impedance
High-impedance
Determined by TRST and / or
TAP controller state
High-impedance
Input
Input
Input
Input
Input
Input
Input
Input
Active during and after reset.
Active HIGH during and after
reset.
Active during and after reset.
Active during and after reset.
Table 7 - Reset State of I/O and Output Pins
Reset State
N / A
N / A
The PTXCLK_SEL bits in the Main Control Register (0000h) are LOW
after reset; PTXCLK is tristated and an input.
N / A
N / A
N / A
N / A
N / A
N / A
RESET LOW forces this pin HIGH. After reset, this pin goes LOW.
N / A
N / A
N / A
In Motorola mode, pin drives HIGH during reset. In Intel mode, drives LOW
during reset.
The interrupt enable bits in the Main Control Register at 0000h are reset to
zero; interrupts are masked after reset.
N / A
N / A
The GENOE bit in the TDM Interface Control Register (6000h) is LOW
after reset; these TDM data pins are tristated and in loopback mode.
The CLKMASTER bit in the TDM Bus Type Register (6010h) resets to ‘0’;
the MT90500 is TDM Slave, and CLKx1 is input from the TDM bus.
The CLKMASTER bit in the TDM Bus Type Register (6010h) resets to ‘0’;
the MT90500 is TDM Slave and FSYNC is input from the TDM bus.
The TDM I/O Register at 6004h resets to all zeroes; all CORSIGxCNF are
set to “00” and all CORSIGx pins are configured as inputs.
See CORSIGA.
See CORSIGA.
See CORSIGA.
See CORSIGA.
The SEC8KEN bit in the Master Clock Generation Control Register
(6090h) resets to ‘0’; SEC8K is an input.
Due to the reset values of the Master Clock Generation Control Register
(6090h) and the Master Clock / CLKx2 Division Factor (6092h),
REF8KCLK is initially equal to MCLK / 8194.
The FREERUN bits in the Master Clock Generation Control Register at
6090h are “00” after reset; the FREERUN pin is reset to active HIGH.
N / A
N / A
Additional Control Information