MT90500 Mitel Semiconductor, MT90500 Datasheet - Page 114

• Manufacturer Part Number: MT90500
• Description: Multi-Channel ATM AAL1 SAR
• Manufacturer: Mitel Semiconductor

MT90500
6.2
6.2.1
114
Clock Skew - CLKx2PO falling to CLKx1 change
CLKx2PO - Output Clock Period
CLKx2PO Pulse Width (HIGH / LOW)
CLKx1 - Output Clock Period
CLKx1 Pulse Width (HIGH / LOW)
Frame Pulse Width
Frame Pulse Delay
Positive: CLKx2PO falling to FSYNC rising
Negative: CLKx2PO rising to FSYNC falling
2.048 Mbps bus (4.096 MHz clock)
4.096 Mbps bus (8.192 MHz clock)
8.192 Mbps bus (16.384 MHz clock)
2.048 Mbps bus (4.096 MHz clock)
4.096 Mbps bus (8.192 MHz clock)
8.192 Mbps bus (16.384 MHz clock)
2.048 Mbps
4.096 Mbps
8.192 Mbps
2.048 Mbps
4.096 Mbps
8.192 Mbps
Positive Frame Pulse - 2.048 Mbps
Negative Frame Pulse - 2.048 Mbps
Positive Frame Pulse - 4.096 Mbps
Negative Frame Pulse - 4.096 Mbps
Positive Frame Pulse - 8.192 Mbps
Negative Frame Pulse - 8.192 Mbps
CLKx2PO
CLKx1
FSYNC (neg.)
FSYNC (pos.)
STi/o
AC Characteristics
Main TDM Bus
Characteristic
Table 77 - Main TDM Bus Output Clock Parameters
Bit 1, Last Channel
Figure 39 - Nominal TDM Bus Timing
t
t
Cx2H/L
Cx1H/L
t
t
Sym
t
t
Cx2P
Cx1P
FPW
t
FPD
SK
Bit 0, Last Channel
26.5
Min
118
240
118
57
57
-2
-2
0
0
30.5
Typ
244
122
122
488
244
122
244
122
488
244
244
122
122
61
61
61
61
Bit 7, Channel 0
Max
34.5
126
248
126
10
20
65
65
10
20
10
20
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Bit 6, Channel 0
C
C
16.39 MHz (61 ns) input
clock with 50/50 duty
cycle
16.39 MHz (61 ns) input
clock
16.39 MHz (61 ns) input
clock
C
C
C
C
L
L
L
L
L
L
= 50 pF
= 200 pF
= 50 pF
= 200 pF
= 50 pF
= 200 pF
Test Conditions
.
.
.
V
V
V
V
V
TT
TT
TT
TT
TT