MT90500 Mitel Semiconductor, MT90500 Datasheet - Page 101

• Manufacturer Part Number: MT90500
• Description: Multi-Channel ATM AAL1 SAR
• Manufacturer: Mitel Semiconductor

Address: 6010 (Hex)
Label: TDMTYP
Reset Value: 0000 (Hex)
CLKMASTER
TDMSMPL
BUSHOLD
TCLKSYN
CLKTYPE
Reserved
Reserved
TDMCLK
CLKALT
TDMFS
Label
Position
15:12
1:0
3:2
5:4
Bit
10
11
6
7
8
9
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/O
Table 50 - TDM Bus Type Register
TDM Fsync type.
When using the positive polarity frame sync, the MT90500 must be in Master mode, or
TCLKSYN (bit<6>) should be LOW, and the SC bus HDLC access will not function (pins
MC, MCRX, MCTX and MCCLK).
TDM Sampling. Determines the sampling point of the serial input bit.
TDM Clock speed. Determines the data rate of the TDM bus (and CLKX1).
Selects source for internal CLKx1.
Note that in TDM Slave mode, with TCLKSYN = ‘1’, the CLKx1 pin is not used as an output
but remains high-impedance. The CABS bit in register 6002h will therefore report a loss of
clocks unless an external signal is present at the CLKx1 pin.
Clock Type. Selects operation of CLKx2 Input when TDM Slave mode is selected (no
effect when TDM Master mode is selected).
TDM Clock Master.
TDM Clock Alternate.
The Clock Master Alternate will become the Clock Master and drive the clock lines only if
the clock fail status bit (CFAIL in 6002h) is HIGH. Note: This bit is only used when
CORSIGACNF in 6004h is “11”, indicating that the CORSIGA pin is configured as
CLKFAIL input (SCSA mode).
Reserved. Must always be set to ‘0’.
BUS Hold Time.
Reserved. Always read as “0000”.
“00” = negative polarity for half-cycle of CLKx1, straddling the frame boundary (SCSA/
MVIP/H-MVIP/ST-BUS);
“01” = Reserved;
“10” = Reserved;
“11” = positive polarity for full-cycle of CLKx1, preceding the frame boundary (IDL).
“00” = 4/4;
“01” = 3/4;
“10” = 2/4;
“11” = Reserved.
“00” = 2 MHz, 32 time slots/frame;
“01” = 4 MHz, 64 time slots/frame;
“10” = 8 MHz, 128 time slots/frame;
”11” = Reserved.
‘0’ = normal CLKx1 output operation as TDM Master, normal CLKx1 input operation as
TDM Slave;
‘1’ = derive CLKx1 from CLKx2 (Slave mode where no CLKx1 is provided by TDM bus)
‘0’ = single-ended input (one input pin: CLKx2);
‘1’ = differential input (two input pins: CLKx2PI and CLKx2NI).
‘0’ = MT90500 is TDM Slave, and does not drive TDM clock pins (CLKx2 is an input);
‘1’ = MT90500 is TDM Master, and drives the TDM clock pins (MT90500 drives CLKx2,
CLKx1, and FSYNC).
‘0’ = disabled;
‘1’ = MT90500 is designated as Clock Master Alternate
‘0’ = fast bus (SCSA 8 Mbps);
‘1’ = slow bus (MVIP / SCSA2 / IDL / ST-BUS)
Description
MT90500
101