MT90500 Mitel Semiconductor, MT90500 Datasheet - Page 57

• Manufacturer Part Number: MT90500
• Description: Multi-Channel ATM AAL1 SAR
• Manufacturer: Mitel Semiconductor

4.4
Figure 30 at the end of this section gives an overview of the processes explained below.
4.4.1
The RX_SAR block performs cell identification and reassembly functions on data moving from the Primary
UTOPIA Port (refer to Section 4.5) toward the TDM interface. The RX_SAR module receives cells from the
UTOPIA module, which has the capability of identifying cells as either CBR cells or non-CBR data cells. When
non-CBR data cells are received by the UTOPIA module, they are stored in a multi-cell circular buffer located in
external memory. When CBR cells are detected (AAL1, CBR-AAL5 or CBR-AAL0), they are processed and the
payload is extracted and stored in time slot-related circular buffers, the size of which can be individually
programmed by software on a per-VC basis.
The RX_SAR block supports AAL1-SDT, pointerless AAL1 structured data transfer (for ITU I.363.1 voiceband
signal transport) and AAL0 cell formats. CBR-AAL5 cells are treated as partially-filled AAL0. Single or multiple
(up to 122) TDM channels are supported per Virtual Circuit (specific VPI/VCI). On the receive side, the
MT90500 RX_SAR block has the ability to receive and process up to 1024 Virtual Circuits simultaneously (and
up to 1024 TDM channels at 64 kbps), resulting in a total of about 74 Mbps of bandwidth on the receive side. If
1024 TDM channels are used for full-duplex connections such as phone calls, the bandwidth will be ~74 Mbps
per direction.
The amount of external memory required for the handling of receive VCs is variable and is defined by the user.
The external memory requirements to support the RX_SAR are scalable and depend mainly on the number of
TDM channels that need to be received on the ATM link and the size of the receive circular buffer required to
compensate for latency and CDV (cell delay variation). As an example, the reception of 1024 simultaneous
Virtual Circuits, each representing a 64 kbps channel, each with a 128 ms buffer, requires external memory
capacity exceeding 1024 Kbytes (SRAM).
The RX_SAR module has no interface to the external pins. It has internal connections to the External Memory
Controller, the UTOPIA module, and the Microprocessor Interface. It also receives synchronization signals from
the TDM module. No fatal errors can be generated by the RX_SAR. Most of the registers associated with it are
targeted at network statistics and error monitoring.
4.4.2
As explained in Section 4.5, detailing the operation of the UTOPIA module, cells received over the ATM link that
are intended for the RX_SAR are tagged and forwarded to the RX_SAR module. For the traffic tagged as CBR,
the RX_SAR then uses control information in the RX_SAR Control Structures to extract the payload data from
the received cell and store it into TDM channel RX Circular Buffers located in external memory. For the traffic
tagged as non-CBR data, the RX_SAR simply stores the whole cell, which is considered to be a raw AAL0 cell,
in a circular FIFO located at the address specified by the Receive Data Cell FIFO Base Address Register
(4020h). This will be explained further in Section 4.5.4. In addition, timing reference cells (which may carry
CBR traffic or non-CBR data) can also be received on the ATM side of the MT90500. As outlined more fully in
Section 4.5.3, the reception of these cells results in the generation of timing pulses used in Adaptive Clock
Recovery.
For each VC assigned to CBR traffic in reception, an RX_SAR Control Structure has to be set up and
maintained in external memory, as explained below.
The RX_SAR Module
RX_SAR Overview
RX_SAR Process
MT90500
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