MT90500 Mitel Semiconductor, MT90500 Datasheet - Page 151

• Manufacturer Part Number: MT90500
• Description: Multi-Channel ATM AAL1 SAR
• Manufacturer: Mitel Semiconductor

7.4.3 External Memory Bandwidth Requirements
The following section provides estimated external memory bandwidth requirements to support the functionality
of the MT90500, excluding negligible non-CBR traffic (i.e. data cells or OAM cells). The following scenarios are
examined: 256, 512, and 1024 bidirectional TDM channels. The memory clock MEMCLK is tied to the input
MCLK, which also clocks all internal processes, and also controls CPU access speed.
ATM Transmit Process Bandwidth
A. Access to TX Circular Buffer Control Structure.
One word read access is required per TDM channel every 4 frames. Thus, one double-word access can
retrieve 2 TDM channels every 4 frames (500 s):
(1 double-word read access / (2 channels * 500 s)) * ‘N’ TDM channels = 1000 * ‘N’ accesses/s.
B. Access to the Transmit Circular Buffers.
One double word (32-bit) write access is required to transfer a TDM channel into a circular buffer every four
frames (500 s). As well, four additional read accesses are required to retrieve the data byte by byte:
((1 double-word write access + 4 half-word read accesses) / 500 s) * ‘N’ TDM channels = 10000 * ‘N’
accesses/s.
C. Access to Transmit Event Schedulers.
Assuming that we have selected 16 VC Pointers (one word each) per frame, we require eight double-word read
accesses per scheduler per frame (125 s):
(8 double-word read accesses / 125 s) * ‘N’ event schedulers = 64000 * ‘N’ accesses/s.
D. Transmit Control Structure Accesses.
Each cell transmitted requires three control double-word read accesses (for the twelve bytes of control data at
the start of each Transmit Control Structure), one control double-word write access (to update the Current
Entry, Sequence Number, and Circular Buffer Pointer fields of the Transmit Control Structure), as well as up to
24 double-word read accesses (to select up to 48 TDM Circular Buffer addresses per cell) to know which data
to transfer, for a total of up to 28 memory accesses per cell transmitted. 256 TDM channels represent a rate of
~ 5.5 cells / 125 s; 512 TDM channels represent a rate of ~11 cells / 125 s; etc.
(28 double-word memory accesses * estimated cell arrival rate (per 125 s) = 224000 * cell arrival rate.
* The case of one TDM channel per cell has been optimized to outperform the standards stated herein. The
case of VCs having odd numbers of TDM channels is slightly worse than the number given.
Sub-total external memory access bandwidth requirements to support the TDM to ATM transmit
process:
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Minimum requirements:
Maximum requirements:
256 TDM channels
512 TDM channels
1024 TDM channels
256 TDM channels
512 TDM channels
1024 TDM channels
1 scheduler
3 schedulers
256 TDM channels
512 TDM channels
1024 TDM channels
~ 4.11 M accesses / sec
~ 16.4 M accesses / sec
0.256 M accesses / s
0.512 M accesses / s
1.024 M accesses / s
2.56 M accesses / s
5.12 M accesses / s
10.24 M accesses / s
0.064 M accesses / s
0.192 M accesses / s
1.232 M accesses / s
2.464 M accesses / s
4.928 M accesses / s
MT90500
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