MT90500 Mitel Semiconductor, MT90500 Datasheet - Page 51

• Manufacturer Part Number: MT90500
• Description: Multi-Channel ATM AAL1 SAR
• Manufacturer: Mitel Semiconductor

age of -1 (i.e. it hasn’t arrived at the MT90500 yet). Thus, in the case of a single channel AAL1-SDT VC, the
software must initialize the value of the Circ. Buf. Pnt. to at least 47, ensuring that at least 47 bytes are
available for cell assembly when the scheduler is ready to transmit an event. This will also ensure that the most
recent 47 bytes of data are sent. A value greater than 56, however, is not recommended because the oldest
data to be sent in a cell may be overwritten by the TDM module and replaced by new data. A value of 51 to 56
is recommended for any single channel AAL1 or CBR-AAL0 fully-filled cell. When using hyper-channels or
+0A
+0C
+0E
+FC
+F8
+FA
+FE
+00
+02
+04
+06
+08
+10
+12
+14
+16
Note: Transmit Control Structures must start on
16-byte boundaries and cannot overlap 256-byte
boundaries.
Pointer to Start of Transmit Control Structure
20
(from 2040)
TXBASE
15
V
V
V
V
V
V
V
V
V
V
VPI(11:8)
GFC /
Current Entry
First Entry
16 15
Figure 16 - Transmit Control Structure Format (AAL1 & CBR-AAL0)
HEC
Offset
TX Circular Buffer Address
TX Circular Buffer Address
TX Circular Buffer Address
TX Circular Buffer Address
TX Circular Buffer Address
TX Circular Buffer Address
TX Circular Buffer Address
TX Circular Buffer Address
TX Circular Buffer Address
TX Circular Buffer Address
TX Struct Pointer (see
Minimum Structure
Size - 14 bytes
Maximum Structure
Size - 256 bytes
VCI(11:0)
Figure 15)
VPI(7:0)
(bits<20:6>)
(bits<20:6>)
(bits<20:6>)
(bits<20:6>)
(bits<20:6>)
(bits<20:6>)
(bits<20:6>)
(bits<20:6>)
(bits<20:6>)
(bits<20:6>)
A
SEQ
8
R S 00
AS
7
Last Entry
Payload Size
Circ. Buf. Pnt.
VCI(15:12)
4
PTI
PSEL
3
0 0 0 0
C1
0
0
First Entry: indicates location of the first TX Circular Buffer Address within the
Transmit Control Structure (lower bits are always 110).
A: Structure Active bit. ‘0’ = inactive; ‘1’ = active.
Last Entry: indicates where last TX Circular Buffer Address is located within the
Transmit Control Structure.
HEC: HEC value (optional).
AS: AAL Type. “00”= CBR-AAL0/AAL5; “01”=Reserved; “10”=AAL1; “11”=AAL1-
SRTS
Payload Size: Indicates the number of payload bytes within an ATM cell. Full
cell = 2Fh. Partially-filled cells = 03h to 2Eh.
Current Entry: indicates location of the current Transmit Circular Buffer. Must be
initialized to First Entry value and is incremented by hardware.
SEQ: Indicates AAL1 sequence number. Possible sequence values are “000” to
“111”. Must be initialized by software to “000”.
Circ. Buf. Pnt: This field must be initialized by software to initial offset required
between TX_SAR Read Pointer and TDM Circular Buffer Write Pointer.
Offset: Offset value between the TDM Circular Buffer Write Pointer and the
TX_SAR Read Pointer is stored in this field. Should be set to initial value of ‘0’.
R: Reserved (set to ‘0’).
S: Structure Initialized. ‘0’ = uninitialized; ‘1’ = initialized. Must be set as ‘0’ by S/
W.
PSEL: P-Byte Selection. ‘0’ for pointerless AAL1 Structured Data Transfer and
CBR-AAL0; ‘8’ for standardized SDT (see text for more details).
GFC: Cell Header GFC field (UNI).
VPI: Cell Header VPI field.
VCI: Cell Header VCI field.
PTI: Cell Header PTI field. LSB of field, when set to ‘1’, indicates OAM-type cell.
C1: Cell Header CLP bit.
V: TX Circular Buffer Valid Bit. ‘0’ = invalid entry; ‘1’ = valid TX Circular Buffer
address.
TX Circular Buffer Address: This is the upper part of the address that points to
a Transmit Circular Buffer (bits 20:6). The buffer must be located relative to the
TX Circular Buffer Base Address (TXCBBASE) set in register 6044h.
Pointer to Current TX Circular Buffer Entry
Pointer to First TX Circular Buffer Entry
Pointer to Last TX Circular Buffer Entry
Note: Upper Structure Address is obtained from the upper 13
bits (i.e. bits<20:8>) of the Pointer to Start of Transmit Control
Structure.
20
20
20
Upper Structure Address
Upper Structure Address
Upper Structure Address
8
8
8
7
7
7
First Entry
Current Entry
Last Entry
0
0
0
0
0
0
MT90500
51