MT90500 Mitel Semiconductor, MT90500 Datasheet - Page 109

• Manufacturer Part Number: MT90500
• Description: Multi-Channel ATM AAL1 SAR
• Manufacturer: Mitel Semiconductor

Address: 60A8 (Hex)
Label: DIVX
Reset Value: 2000 (Hex)
Address: 60AA (Hex)
Label: DIVXR
Reset Value: 0FFF (Hex)
Address: 60B0(Hex)
Label: SRTGD
Reset Value: 0000 (Hex)
TX_Ch_per_VC
TX_Gapping
Reserved
Reserved
Reserved
DIVXN
Label
Label
Label
DIVX
Bit Position
Bit Position
Bit Position
15:14
15:12
13:0
11:0
14:8
7:0
15
Table 69 - SRTS Transmit Gapping Divider Register
Type
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
This value is used (along with DIVXN, in the next register) to divide MCLK to obtain an
RXVCLK reference. The average frequency of RXVCLK is obtained as follows:
Note that when a new RXVCLK setting requires a change to this register and to the DIVX
Ratio Register, these two writes should be performed as closely together as possible. This
is required to prevent drifting of the REF8KCLK output frequency during the period that
one register has been updated but the other hasn’t.
Reserved. Should be written as “00”.
This value defines how many times MCLK will be divided by (DIVX + 2) and how many
times it will be divided by (DIVX + 3), as per the formula shown in 60A8h above. When
001h, MCLK is divided by (DIVX + 2) once, then divided 4095 times by (DIVX + 3).
Note: 0 is an illegal value for DIVXN (same ratio as 1)
Reserved. Should be written as “0000”.
This field provides the separation between consecutive pulses of the f
should be set according to the following formula: (256 / number of channels per VC) - 1.
The result must be rounded down.
1 channel -> 255
2 channels -> 127
3 channels -> 84
...
Number of channels in the VC that is selected for transmitting the SRTS.
0h -> 1 channel
1h -> 2 channels
...
79h -> 122 channels
Note: Since maximum number of channels per VC is 122, values 7A:7F are reserved.
Reserved. Should be written as ‘0’.
Table 68 - DIVX Ratio Register
RXVCLKavg
Table 67 - DIVX Register
=
MCLK
------------------------------------------------------------------------------------------------------------------------------- ---------- -
------------------------------------------------------------------------------------------------------------------------------- ---------- -
DIVX
+
Description
Description
Description
2
DIVXN
+
DIVX
4096
1
+
3
MT90500
4096 DIVXN
B
clock. This field
–
109