MT90500 Mitel Semiconductor, MT90500 Datasheet - Page 100

• Manufacturer Part Number: MT90500
• Description: Multi-Channel ATM AAL1 SAR
• Manufacturer: Mitel Semiconductor

MT90500
100
Address: 6004 (Hex)
Label: CORSIG
Reset Value: 0000 (Hex)
CORSIGACNF
CORSIGBCNF
CORSIGCCNF
CORSIGDCNF
CORSIGECNF
CORSIGC
CORSIGD
CORSIGA
CORSIGB
CORSIGE
Reserved
Label
Bit Position
1:0
3:2
5:4
7:6
9:8
10
11
12
13
14
15
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CORSIGA Configuration. Selects operation of the CORSIGA pin.
CORSIGB Configuration.
CORSIGC Configuration.
CORSIGD Configuration.
CORSIGE Configuration.
Reserved. Should be set to ‘0’.
Value that will be driven on CORSIGA output pin (only applicable if CORSIGACNF=“01”).
Value that will be driven on CORSIGB output pin (only applicable if CORSIGBCNF=“01”).
Value that will be driven on CORSIGC output pin (only applicable if CORSIGCCNF=“01”).
Value that will be driven on CORSIGD output pin (only applicable if CORSIGDCNF=“01”).
Value that will be driven on CORSIGE output pin (only applicable if CORSIGECNF=“01”).
Table 49 - TDM I/O Register
“00” General I/O pin configured as input (see CORSIGA bit in register 6002h)
“01” General I/O pin configured as programmable output (see CORSIGA bit in this
register)
“10” Reserved
“11” CLKFAIL I/O (see CFAIL at 6002h) - zero driven out when the MT90500 is clock
master; CLKFAIL input from SCSA bus when in slave mode or inactive clock master
alternate.
“00” General I/O pin configured as input
“01” General I/O pin configured as programmable output (see CORSIGB bit in this
register)
“10” MC: I/O for SCSA message channel (RXDATA sent to CORSIGD; TXDATA read
from CORSIGC
“11” FNXI: SRTS FNX Network Clock Input.
“00” General I/O pin configured as input
“01” General I/O pin configured as programmable output (see CORSIGC bit in this
register)
“10” HDLC MCTX: data input for SCSA message channel
“11” SRTS ENA output (there is a valid SRTS bit being transmitted on CORSIGD).
“00” General I/O pin configured as input
“01” General I/O pin configured as programmable output (see CORSIGD bit in this
register)
“10” HDLC MCRX: data output for SCSA message channel
“11” SRTS DATA output from the clock recovery module.
“00” General I/O pin configured as input
“01” General I/O pin configured as programmable output (see CORSIGE bit in this
register)
“10” HDLC MCCLK: clock output for SCSA message channel
“11” Reserved.
Description