MT90500 Mitel Semiconductor, MT90500 Datasheet - Page 73

• Manufacturer Part Number: MT90500
• Description: Multi-Channel ATM AAL1 SAR
• Manufacturer: Mitel Semiconductor

CLKx1
ATM Physical Layer
Network Clock
A 4-bit RTS value is generated once every “period of the RTS” (T
bits in each 8-cell sequence, the “period of the RTS” is the assembly time of 8 cells on the designated SRTS
VC. The SRTS Transmit Byte Counter Register at 60B2h contains the number of payload bytes within an 8-cell
sequence of the SRTS VC. The value in this register is used to divide the byte frequency f
“period of the RTS”. For pointerless AAL1 Structured Data Transfer, the number of bytes necessary to fill 8 cells
is 376 (8 cells @ 47 bytes per cell). In Nx64 AAL1 SDT, the number of bytes required to fill 8 cells varies
depending on the number of P-bytes sent within an 8-cell sequence, but it is generally set to 375 bytes (1 cell
of 46 TDM payload bytes plus 7 cells of 47 TDM payload bytes). The SRTS Transmit Divider Register shown in
Figure 33 generates a latch pulse which captures the value of a free-running counter clocked by the external
signal f nx (the network reference clock, input at the FNXI pin). The latched value is the four-bit residual time
stamp. Multiple latches (a 5-deep FIFO) are used to synchronize this clocking block with cell transmission
(controlled by the transmit event schedulers).
In order for the SRTS clock recovery method to operate correctly, the divided-down network clock, FNXI, must
be properly derived. As stated in I.363.1:
For example, to support N = 24 (f
be 2.430 MHz (8000 * 19440 / 2
75.9375 kHz (8000 * 19440 / 2
In compliance with I.363.1, the MT90500 transmits the 4-bit RTS values in the serial bit stream provided by the
CSI bits of successive odd-sequence-numbered SAR-PDU headers (the even-numbered CSI bits are available
for other uses such as SDT pointers). The modulo-8 sequence count provides a frame structure over 8 bits in
this serial bit stream. The MSB of the RTS is placed in the CSI bit of the SAR-PDU header with a sequence
count of 1.
Due to the internal hardware design of the MT90500, the frequency of FNXI must be < MCLK / 3. This places
no restrictions on the SRTS VC as long as MCLK is greater than 30 MHz. Since the maximum structure size is
122 channels, the maximum value of f
Gapping Control
f
“For SDH and non-SDH physical layers, a clock at frequency f
network clock, is available from which clocks at frequencies
can be derived. This set of derived frequencies can accommodate all service rates from 64 kbps up to
the full capacity of the STM-1 payload. The exact value of f
frequency ratio is constrained by 1
B
SRTS Transmit Divider Register
Generator
f
B
= f
S
/ 8 = service byte clock
f
B
Divide by x
Byte Counter
11
f
nx
).
S
6
= f
= 1.536 MHz) or N = 32 (f
). To support N = 1 (f
8
Figure 33 - Transmit SRTS Operation
S
x (19440 / 2
= 7.808 MHz, and the maximum value of f
FNXI
period of the RTS
(one 8-cell cycle)
f
nx
/f
k
s
) kHz, where k = 0,1,2,...,12
< 2.”
f
nx
S
= 64 kbps), the derived network frequency will be
S
= 2.048 MHz), the derived network frequency will
clk
N
4-bit counter
data_in
). Since one RTS value is carried by the CSI
LATCHES
MULTIPLE
nx
4
to be used is uniquely specified since the
8
= 8 kHz, synchronized to a common
Internal to MT90500
enable
nx
RTS
4
is 9.72 MHz.
TX_SAR
BLOCK
MT90500
B
to obtain the
Transmit
ATM Cells
w/ CSI b
73
its