upd78f0114hgb-8es-a Renesas Electronics Corporation., upd78f0114hgb-8es-a Datasheet - Page 113

• Manufacturer Part Number: upd78f0114hgb-8es-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

clocks in each operation status and between the oscillation control flag and oscillation status of each clock are shown
in Tables 5-3 and 5-4, respectively.
f
R
: Oscillation stopped
A status transition diagram of this product is shown in Figure 5-15, and the relationship between the operation
CPU clock: f
f
XP
Notes 1.
: Oscillating
Status 4
2.
3.
4.
5.
(1) When “internal oscillator can be stopped by software” is selected by option byte
XP
When shifting from status 3 to status 4, make sure that bit 1 (MCS) of the main clock mode register
(MCM) is 1.
Before shifting from status 2 to status 3 after reset and STOP are released, check the high-speed
system clock oscillation stabilization time status using the oscillation stabilization time counter status
register (OSTC).
Waiting for the oscillation stabilization time is not required when the external RC oscillation clock is
selected as the high-speed system clock by the option byte. Therefore, the CPU clock can be
switched without reading the OSTC value.
When shifting from status 2 to status 1, make sure that MCS is 0.
When “internal oscillator can be stopped by software” is selected by the option byte, the watchdog
timer stops operating in the HALT and STOP modes, regardless of the source clock of the watchdog
timer. However, oscillation of internal oscillator does not stop even in the HALT and STOP modes if
RSTOP = 0.
All reset sources (RESET input, POC, LVI, clock monitor, and WDT)
RSTOP = 1
RSTOP = 0
instruction
Interrupt
HALT
instruction
STOP
Interrupt
Note 1
Figure 5-15. Status Transition Diagram (1/4)
CPU clock: f
f
f
XP
R
: Oscillating
: Oscillating
Status 3
STOP
instruction
(when subsystem clock is not used)
Interrupt
CHAPTER 5 CLOCK GENERATOR
User’s Manual U16961EJ4V0UD
XP
Interrupt
HALT
instruction
MCM0 = 1
MCM0 = 0
STOP
HALT
instruction
Interrupt
Note 4
Note 4
STOP
Note 2
f
CPU clock: f
f
XP
R
Interrupt
: Oscillating
: Oscillating
Status 2
HALT
instruction
HALT instruction
R
instruction
Interrupt
Reset
MSTOP = 1
Reset release
STOP
MSTOP = 0
Note 5
Interrupt
Note 3
f
XP
: Oscillation stopped
CPU clock: f
f
R
: Oscillating
Status 1
R
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