upd78f0114hgb-8es-a Renesas Electronics Corporation., upd78f0114hgb-8es-a Datasheet - Page 481

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upd78f0114hgb-8es-a

Manufacturer Part Number
upd78f0114hgb-8es-a
Description
8-bit Single-chip Microcontrollers
Manufacturer
Renesas Electronics Corporation.
Datasheet

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16-Bit
Timer/
Event
Counter
00
Function
Capture/
compare control
register 00
(CRC00)
16-bit timer
output control
register 00
(TOC00)
Prescaler mode
register 00
(PRM00)
16-bit timer
capture/compar
e register 010
(CR010)
Details of
Function
Timer operation must be stopped before setting CRC00.
When the mode in which clear & start occurs on a match between TM00 and
CR000 is selected with 16-bit timer mode control register 00 (TMC00), CR000
should not be specified as a capture register.
To ensure that the capture operation is performed properly, the capture trigger
requires a pulse longer than two cycles of the count clock selected by prescaler
mode register 00 (PRM00).
Timer operation must be stopped before setting other than TOC004.
If LVS00 and LVR00 are read, 0 is read.
OSPT00 is automatically cleared after data is set, so 0 is read.
Do not set OSPT00 to 1 other than in one-shot pulse output mode.
A write interval of two cycles or more of the count clock selected by prescaler
mode register 00 (PRM00) is required to write to OSPT00 successively.
Do not set LVS00 to 1 before TOE00, and do not set LVS00 and TOE00 to 1
simultaneously.
Perform <1> and <2> below in the following order, not at the same time.
When the internal oscillation clock is selected as the clock to be supplied to the
CPU, the clock of the internal oscillator is divided and supplied as the count clock.
If the count clock is the internal oscillation clock, the operation of 16-bit
timer/event counter 00 is not guaranteed. When an external clock is used and
when the internal oscillation clock is selected and supplied to the CPU, the
operation of 16-bit timer/event counter 00 is not guaranteed, either, because the
internal oscillation clock is supplied as the sampling clock to eliminate noise.
Always set data to PRM00 after stopping the timer operation.
If the valid edge of the TI000 pin is to be set for the count clock, do not set the
clear & start mode using the valid edge of the TI000 pin and the capture trigger.
If the TI000 or TI010 pin is high level immediately after system reset, the rising
edge is immediately detected after the rising edge or both the rising and falling
edges are set as the valid edge(s) of the TI000 pin or TI010 pin to enable the
operation of 16-bit timer counter 00 (TM00). Care is therefore required when
pulling up the TI000 or TI010 pin. However, when re-enabling operation after the
operation has been stopped, the rising edge is not detected if the TI000 or TI010
pin is the high level.
When the valid edge of the TI010 pin is used, P01 cannot be used as the timer
output pin (TO00). When P01 is used as the TO00 pin, the valid edge of the
TI010 pin cannot be used.
To change the value of the duty factor (the value of the CR010 register) during
operation, see Caution 2 in Figure 6-15 PPG Output Operation Timing.
<1> Set TOC001, TOC004, TOE00, OSPE00: Timer output operation setting
<2> Set LVS00, LVR00:
APPENDIX D LIST OF CAUTIONS
User’s Manual U16961EJ4V0UD
Timer output F/F setting
Cautions
p. 132
p. 132
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