upd78f0114hgb-8es-a Renesas Electronics Corporation., upd78f0114hgb-8es-a Datasheet - Page 488

• Manufacturer Part Number: upd78f0114hgb-8es-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

488
A/D
Converter
Function
Analog input
channel
specification
register (ADS)
A/D conversion
result register
(ADCR)
Power-fail
comparison
mode register
(PFM)
Power-fail
comparison
threshold
register (PFT)
A/D conversion
operation
Power-fail
detection
function
Operating
current in
standby mode
Input range of
ANI0 to ANI7
Details of
Function
Be sure to clear bits 3 to 7 of ADS to 0.
If data is written to ADS, a wait cycle is generated. Do not write data to ADS when
the CPU is operating on the subsystem clock and the high-speed system clock is
stopped. For details, see CHAPTER 30 CAUTIONS FOR WAIT.
When writing to the A/D converter mode register (ADM) and analog input channel
specification register (ADS), the contents of ADCR may become undefined. Read
the conversion result following conversion completion before writing to ADM and
ADS. Using timing other than the above may cause an incorrect conversion result
to be read.
If data is read from ADCR, a wait cycle is generated. Do not read data from
ADCR when the CPU is operating on the subsystem clock and the high-speed
system clock is stopped. For details, see CHAPTER 30 CAUTIONS FOR WAIT.
If data is written to PFM, a wait cycle is generated. Do not write data to PFM
when the CPU is operating on the subsystem clock and the high-speed system
clock is stopped. For details, see CHAPTER 30 CAUTIONS FOR WAIT.
If data is written to PFT, a wait cycle is generated. Do not write data to PFT when
the CPU is operating on the subsystem clock and the high-speed system clock is
stopped. For details, see CHAPTER 30 CAUTIONS FOR WAIT.
Make sure the period of <1> to <3> is 14 s or more.
It is no problem if the order of <1> and <2> is reversed.
<1> can be omitted. However, do not use the first conversion result after <3> in
this case.
The period from <4> to <7> differs from the conversion time set using bits 5 to 3
(FR2 to FR0) of ADM. The period from <6> to <7> is the conversion time set
using FR2 to FR0.
Make sure the period of <3> to <6> is 14 s or more.
It is no problem if order of <3>, <4>, and <5> is changed.
<3> must not be omitted if the power-fail function is used.
The period from <7> to <11> differs from the conversion time set using bits 5 to 3
(FR2 to FR0) of ADM. The period from <9> to <11> is the conversion time set
using FR2 to FR0.
The A/D converter stops operating in the standby mode. At this time, the operating
current can be reduced by clearing bit 7 (ADCS) and bit 0 (ADCE) of the A/D
converter mode register (ADM) to 0 (see Figure 11-2).
Observe the rated range of the ANI0 to ANI7 input voltage. If a voltage of AV
or higher and AV
input to an analog input channel, the converted value of that channel becomes
undefined. In addition, the converted values of the other channels may also be
affected.
APPENDIX D LIST OF CAUTIONS
User’s Manual U16961EJ4V0UD
SS
or lower (even in the range of absolute maximum ratings) is
Cautions
REF
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