upd78f0114hgb-8es-a Renesas Electronics Corporation., upd78f0114hgb-8es-a Datasheet - Page 275

• Manufacturer Part Number: upd78f0114hgb-8es-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

<R>
(4) Clock selection register 6 (CKSR6)
Address: FF56H After reset: 00H R/W
Notes 1.
Cautions 1. When the internal oscillation clock is selected as the clock to be supplied to the CPU, the
Symbol
CKSR6
This register selects the base clock of serial interface UART6.
CKSR6 can be set by an 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Remark CKSR6 can be refreshed (the same value is written) by software during a communication operation
2.
(when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6
= 1).
Be sure to set the base clock so that the following condition is satisfied.
Note the following points when selecting the TM50 output as the base clock.
It is not necessary to enable the TO50 pin as a timer output pin in any mode.
TPS63
V
V
V
V
PWM mode (TMC506 = 1)
Start the operation of 8-bit timer/event counter 50 first and then set the base clock to make the duty =
50%.
Mode in which the base clock is cleared and started upon a match of TM50 and CR50 (TMC506 = 0)
Start the operation of 8-bit timer/event counter 50 first and then enable the timer F/F inversion
operation (TMC501 = 1).
clock of the internal oscillator is divided and supplied as the count clock. If the base clock is
the internal oscillation clock, the operation of serial interface UART6 is not guaranteed.
DD
DD
DD
DD
7
0
0
0
0
0
0
0
0
0
1
1
1
1
= 4.0 to 5.5 V: Base clock
= 3.3 to 4.0 V: Base clock
= 2.7 to 3.3 V: Base clock
= 2.5 to 2.7 V: Base clock
Figure 13-8. Format of Clock Selection Register 6 (CKSR6)
TPS62
Other than above
6
0
0
0
0
0
1
1
1
1
0
0
0
0
CHAPTER 13 SERIAL INTERFACE UART6
TPS61
5
0
0
0
1
1
0
0
1
1
0
0
1
1
User’s Manual U16961EJ4V0UD
2.5 MHz (standard products, (A) grade products only)
10 MHz
8.38 MHz
5 MHz
TPS60
4
0
0
1
0
1
0
1
0
1
0
1
0
1
f
f
f
f
f
f
f
f
f
f
f
TM50 output
Setting prohibited
X
X
X
X
X
X
X
X
X
X
X
/2 (5 MHz)
/2
/2
/2
/2
/2
/2
/2
/2
/2
(10 MHz)
TPS63
2
3
4
5
6
7
8
9
10
(2.5 MHz)
(1.25 MHz)
(625 kHz)
(312.5 kHz)
(156.25 kHz)
(78.13 kHz)
(39.06 kHz)
(19.53 kHz)
(9.77 kHz)
3
Base clock (f
Note 2
TPS62
2
XCLK6
) selection
TPS61
1
Note 1
TPS60
0
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