upd78f0114hgb-8es-a Renesas Electronics Corporation., upd78f0114hgb-8es-a Datasheet - Page 484

• Manufacturer Part Number: upd78f0114hgb-8es-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

484
16-Bit
Timer/
Event
Counter
00
8-Bit
Timer/
Event
Counters
50 and 51
Function
Capture
operation
Compare
operation
Edge detection
8-bit timer
compare
register 5n
(CR5n)
Timer clock
selection
register 50
(TCL50)
Timer clock
selection
register 51
(TCL51)
Details of
Function
If the TI000 pin valid edge is specified as the count clock, a capture operation by
the capture register specified as the trigger for the TI000 pin is not possible.
To ensure that the capture operation is performed properly, the capture trigger
requires a pulse two cycles longer than the count clock selected by prescaler
mode register 00 (PRM00).
The capture operation is performed at the falling edge of the count clock. An
interrupt request input (INTTM000/INTTM010), however, is generated at the rise
of the next count clock.
A capture operation may not be performed for CR000/CR010 set in compare
mode even if a capture trigger has been input.
If the TI000 or TI010 pin is high level immediately after system reset and the rising
edge or both the rising and falling edges are specified as the valid edge of the
TI000 or TI010 pin to enable the 16-bit timer counter 00 (TM00) operation, a rising
edge is detected immediately after the operation is enabled. Be careful therefore
when pulling up the TI000 or TI010 pin. However, the rising edge is not detected
at restart after the operation has been stopped if the TI000 or TI010 pin is the high
level.
The sampling clock used to eliminate noise differs when the TI000 pin valid edge
is used as the count clock and when it is used as a capture trigger. In the former
case, the count clock is f
prescaler mode register 00 (PRM00). The capture operation is only performed
when a valid level is detected twice by sampling the valid edge, thus eliminating
noise with a short pulse width.
In the mode in which clear & start occurs on a match of TM5n and
CR5n (TMC5n6 = 0), do not write other values to CR5n during operation.
In PWM mode, make the CR5n rewrite interval 3 count clocks of the count clock
(clock selected by TCL5n) or more.
When the internal oscillation clock is selected as the clock to be supplied to the
CPU, the clock of the internal oscillator is divided and supplied as the count clock.
If the count clock is the internal oscillation clock, the operation of 8-bit timer/event
counter 50 is not guaranteed.
When rewriting TCL50 to other data, stop the timer operation beforehand.
Be sure to clear bits 3 to 7 to 0.
When the internal oscillation clock is selected as the clock to be supplied to the
CPU, the clock of the internal oscillator is divided and supplied as the count clock.
If the count clock is the internal oscillation clock, the operation of 8-bit timer/event
counter 51 is not guaranteed.
When rewriting TCL51 to other data, stop the timer operation beforehand.
Be sure to clear bits 3 to 7 to 0.
APPENDIX D LIST OF CAUTIONS
User’s Manual U16961EJ4V0UD
X
, and in the latter case the count clock is selected by
Cautions
p. 160
p. 160
p. 160
p. 160
p. 160
p. 160
p. 164
p. 164
p. 165
p. 165
p. 165
p. 166
p. 166
p. 166
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