upd78f0114hgb-8es-a Renesas Electronics Corporation., upd78f0114hgb-8es-a Datasheet - Page 131

• Manufacturer Part Number: upd78f0114hgb-8es-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

Address FFBAH
Symbol
TMC00
TMC003 TMC002 TMC001
OVF00
Cautions 1. Timer operation must be stopped before writing to bits other than the OVF00 flag.
Remark TO00:
0
0
0
0
1
1
1
1
0
1
7
0
Overflow not detected
Overflow detected
0
0
1
1
0
0
1
1
TI000:
TM00:
CR000: 16-bit timer capture/compare register 000
CR010: 16-bit timer capture/compare register 010
2. Set the valid edge of the TI000/P00 pin using prescaler mode register 00 (PRM00).
3. If any of the following modes is selected: the mode in which clear & start occurs on match
6
0
between TM00 and CR000, the mode in which clear & start occurs at the TI000 pin valid edge,
or free-running mode, when the set value of CR000 is FFFFH and the TM00 value changes
from FFFFH to 0000H, the OVF00 flag is set to 1.
After reset: 00H
Figure 6-5. Format of 16-Bit Timer Mode Control Register 00 (TMC00)
0
1
0
1
0
1
0
1
5
0
16-bit timer/event counter 00 output pin
16-bit timer/event counter 00 input pin
16-bit timer counter 00
Operation stop
(TM00 cleared to 0)
Free-running mode
Clear & start occurs on TI000
pin valid edge
Clear & start occurs on match
between TM00 and CR000
4
0
Operating mode and clear
TMC003
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
R/W
mode selection
3
TMC002
16-bit timer counter 00 (TM00) overflow detection
2
User’s Manual U16961EJ4V0UD
TMC001
1
OVF00
<0>
No change
Match between TM00 and
CR000 or match between
TM00 and CR010
Match between TM00 and
CR000, match between TM00
and CR010 or TI000 pin valid
edge
Match between TM00 and
CR000 or match between
TM00 and CR010
Match between TM00 and
CR000, match between TM00
and CR010 or TI000 pin valid
edge
TO00 inversion timing selection
Not generated
<When used as compare
register>
Generated on match between
TM00 and CR000, or match
between TM00 and CR010
<When used as capture
register>
Generated by inputting CR000
capture trigger
Interrupt request generation
131