st7fmc2s7t6 STMicroelectronics, st7fmc2s7t6 Datasheet - Page 115

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st7fmc2s7t6

Manufacturer Part Number
st7fmc2s7t6
Description
8-bit Mcu With Nested Interrupts, Flash, 10-bit Adc, Brushless Motor Control, Five Timers, Spi, Linsci
Manufacturer
STMicroelectronics
Datasheet
LINSCI
10.5.6 Low Power Modes
Mode
WAIT
HALT
SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)
Description
No effect on SCI.
SCI interrupts cause the device to exit from
Wait mode.
SCI registers are frozen.
In Halt mode, the SCI stops transmitting/re-
ceiving until Halt mode is exited.
10.5.7 Interrupts
The SCI interrupt events are connected to the
same interrupt vector (see Interrupts chapter).
These events generate an interrupt if the corre-
sponding Enable Control Bit is set and the inter-
rupt mask in the CC register is reset (RIM instruc-
tion).
Transmit Data Register
Empty
Transmission Com-
plete
Received Data Ready
to be Read
Overrun Error or LIN
Synch Error Detected
Idle Line Detected
Parity Error
LIN Header Detection
Interrupt Event
Event
RDRF
TDRE
LHDF
Flag
IDLE
LHE
OR/
TC
PE
Control
Enable
ST7MC1/ST7MC2
TCIE
LHIE
ILIE
Bit
RIE
PIE
TIE
from
Wait
Exit
Yes
115/308
from
Halt
Exit
No
1

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