st7fmc2s7t6 STMicroelectronics, st7fmc2s7t6 Datasheet - Page 237

• Manufacturer Part Number: st7fmc2s7t6
• Description: 8-bit Mcu With Nested Interrupts, Flash, 10-bit Adc, Brushless Motor Control, Five Timers, Spi, Linsci
• Manufacturer: STMicroelectronics

10-BIT A/D CONVERTER (ADC) (Cont’d)
When a conversion is complete:
To read the 10 bits, perform the following steps:
1. Poll the EOC bit or wait for EOC interrupt
2. Read ADCDRLSB
3. Read ADCDRMSB
The EOC bit is reset by hardware once the AD-
CDRMSB is read.
To read only 8 bits, perform the following steps:
1. Poll the EOC bit or wait for EOC interrupt
2. Read ADCDRMSB
The EOC bit is reset by hardware once the AD-
CDRMSB is read.
Changing the conversion channel
The application can change channels during con-
version. In this case the current conversion is
stopped and the A/D converter starts converting
the newly selected channel.
ADCCR consistency
If an End Of Conversion event occurs after soft-
ware has read the ADCDRLSB but before it has
read the ADCDRMSB, there would be a risk that
the two values read would belong to different sam-
ples.
– The EOC bit is set by hardware
– An interrupt request is generated if the ADCIE
– The result is in the ADCDR registers and re-
bit in the MCCBCR register is set (see
6.4.7 on page
mains valid until the next conversion has end-
ed.
37).
section
To guarantee consistency:
Thus, it is mandatory to read the ADCDRMSB just
after reading the ADCDRLSB. Otherwise the AD-
CDR register will not be updated until the AD-
CDRMSB is read.
10.8.4 Low Power Modes
Note: The A/D converter may be disabled by re-
setting the ADON bit. This feature allows reduced
power consumption when no conversion is need-
ed.
10.8.5 Interrupts
1)
section 6.4.7 on page
Mode
WAIT
HALT
End of Conver-
sion
The ADCIE bit is in the MCCBCR register (see
– The ADCDRMSB and the ADCDRLSB are
– The ADCDRMSB and the ADCDRLSB are un-
Interrupt
locked when the ADCCRLSB is read
locked when the MSB is read or when ADON
is reset.
Event
Description
No effect on A/D Converter
A/D Converter disabled.
After wake up from Halt mode, the A/D
Converter requires a stabilization time
t
before accurate conversions can be
performed.
STAB
Event
EOC
Flag
(see Electrical Characteristics)
37)
ADCIE
Control
Enable
Bit
ST7MC1/ST7MC2
1)
from
Wait
Exit
Yes
from
Exit
Halt
237/308
No