st7fmc2s7t6 STMicroelectronics, st7fmc2s7t6 Datasheet - Page 44

• Manufacturer Part Number: st7fmc2s7t6
• Description: 8-bit Mcu With Nested Interrupts, Flash, 10-bit Adc, Brushless Motor Control, Five Timers, Spi, Linsci
• Manufacturer: STMicroelectronics

ST7MC1/ST7MC2
INTERRUPTS (Cont’d)
7.6 EXTERNAL INTERRUPTS
The pending interrupts are cleared writing a differ-
ent value in the ISx[1:0], IPA or IPB bits of the
EICR.
Note: External interrupts are masked when an I/O
(configured as input interrupt) of the same inter-
rupt vector is forced to V
7.6.1 I/O PORT INTERRUPT SENSITIVITY
The external interrupt sensitivity is controlled by
the IPA, IPB and ISxx bits of the EICR register
(Figure
independent external interrupt source sensitivities.
44/308
1
24). This control allows to have up to 4 fully
SS
.
Each external interrupt source can be generated
on four (or five) different events on the pin:
I
I
I
I
I
To guarantee correct functionality, the sensitivity
bits in the EICR register can be modified only
when the I1 and I0 bits of the CC register are both
set to 1 (level 3).
Falling edge
Rising edge
Falling and rising edge
Falling edge and low level
Rising edge and high level (only for ei0 and ei2)