st7fmc2s7t6 STMicroelectronics, st7fmc2s7t6 Datasheet - Page 69
st7fmc2s7t6
Manufacturer Part Number
st7fmc2s7t6
Description
8-bit Mcu With Nested Interrupts, Flash, 10-bit Adc, Brushless Motor Control, Five Timers, Spi, Linsci
Manufacturer
STMicroelectronics
Datasheet
1.ST7FMC2S7T6.pdf
(308 pages)
- Current page: 69 of 308
- Download datasheet (5Mb)
ON-CHIP PERIPHERALS (Cont’d)
Output compare and Time base interrupt
On overflow, the OVF flag of the ARTCSR register
is set and an overflow interrupt request is generat-
ed if the overflow interrupt enable bit, OIE, in the
ARTCSR register, is set. The OVF flag must be re-
set by the user software. This interrupt can be
used as a time base in the application.
Figure 42. External Event Detector Example (3 counts)
f
EXT
COUNTER
=f
COUNTER
OVF
FDh
FEh
ARTARR=FDh
FFh
INTERRUPT
IF OIE=1
FDh
External clock and event detector mode
Using the f
auto-reload timer can be used as an external clock
event detector. In this mode, the ARTARR register
is used to select the n
be counted before setting the OVF flag.
Caution: The external clock function is not availa-
ble in HALT mode. If HALT mode is used in the ap-
plication, prior to executing the HALT instruction,
the counter must be disabled by clearing the TCE
bit in the ARTCSR register to avoid spurious coun-
ter increments.
ARTCSR READ
FEh
EXT
n
EVENT
FFh
external prescaler input clock, the
INTERRUPT
IF OIE=1
= 256 - ARTARR
EVENT
FDh
ARTCSR READ
ST7MC1/ST7MC2
number of events to
t
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