st7fmc2s7t6 STMicroelectronics, st7fmc2s7t6 Datasheet - Page 301

• Manufacturer Part Number: st7fmc2s7t6
• Description: 8-bit Mcu With Nested Interrupts, Flash, 10-bit Adc, Brushless Motor Control, Five Timers, Spi, Linsci
• Manufacturer: STMicroelectronics

IMPORTANT NOTES (Cont’d)
break. This can be ensured by temporarily disa-
bling interrupts.
The exact sequence is:
- Disable interrupts
- Reset and Set TE (IDLE request)
- Set and Reset SBK (Break Request)
- Re-enable interrupts
LIN mode
If the LINE bit in the SCICR3 is set and the M bit in
the SCICR1 register is reset, the LINSCI is in LIN
master mode. A single break character is sent by
setting and resetting the SBK bit in the SCICR2
register. In some cases, the break character may
have a longer duration than expected:
- 24 bits instead of 13 bits
Occurrence
The occurrence of the problem is random and pro-
portional to the baudrate. With a transmit frequen-
cy of 19200 baud (fCPU=8MHz and SCI-
BRR=0xC9), the wrong break duration occurrence
is around 1%.
Analysis
The LIN protocol specifies a minimum of 13 bits for
the break duration, but there is no maximum value.
Nevertheless, the maximum length of the header
is specified as (14+10+10+1)x1.4=49 bits. This is
composed of:
- the synch break field (14 bits),
- the synch field (10 bits),
- the identifier field (10 bits).
Every LIN frame starts with a break character.
Adding an idle character increases the length of
Figure 168. Header Reception Event Sequence
x x x x x x x x x x x x x
x x x x x x x x x x x x x
x x x x x x x x x x x x x
x x x x x x x x x x x x x
x x x x x x x x x x x x x
x x x x x x x x x x x x x
x x x x x x x x x x x x x
x x x x x x x x x x x x x
x x x x x x x x x x x x x
x x x x x x x x x x x x x
x x x x x x x x x x x x x
x x x x x x x x x x x x x
x x x x x x x x x x x x x
x x x x x x x x x x x x x
x x x x x x x x x x x x x
x x x x x x x x x x x x x
LIN Synch
Break
LIN Synch
Field
T
HEADER
Identifier
Field
each header by 10 bits. When the problem occurs,
the header length is increased by 11 bits and be-
comes ((14+11)+10+10+1)=45 bits.
To conclude, the problem is not always critical for
LIN communication if the software keeps the time
between the sync field and the ID smaller than 4
bits, i.e. 208us at 19200 baud.
The workaround is the same as for SCI mode but
considering the low probability of occurrence (1%),
it may be baetter to keep the break generation se-
quence as it is.
15.3.2 Header Time-out does not prevent wake-
up from mute Mode
Normally, when LINSCI is configured in LIN slave
mode, if a header time-out occurs during a LIN
header reception (i.e. header length > 57 bits), the
LIN Header Error bit (LHE) is set, an interrupt oc-
curs to inform the application but the LINSCI
should stay in mute mode, waiting for the next
header reception.
Problem Description
The LINSCI sampling period is Tbit / 16. If a LIN
Header time-out occurs between the 9th and the
15th sample of the Identifier Field Stop Bit (refer to
Figure
mode. Nevertheless, LHE is set and LIN Header
Detection Flag (LHDF) is kept cleared.
In addition, if LHE is reset by software before this
15th sample (by accessing the SCISR register and
reading the SCIDR register in the LINSCI interrupt
routine), the LINSCI will generate another LINSCI
interrupt (due to the RDRF flag setting).
168), the LINSCI wakes up from mute
ID field STOP bit
Active mode is set
(RWU is cleared)
ST7MC1/ST7MC2
Critical
Window
RDRF flag is set
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