mg84fl54 Megawin Technology, mg84fl54 Datasheet - Page 53

• Manufacturer Part Number: mg84fl54
• Description: Full-speed Usb Micro-controller
• Manufacturer: Megawin Technology

ensures that if the instruction in progress is RETI or any write to the registers associated the interrupts, then at
least one more instruction will be executed before any interrupt is vectored to.
The polling cycle is repeated with each instruction cycle, and the values polled are the values that were present
in the previous instruction cycle. If the interrupt flag for a level-sensitive external interrupt is active but not being
responded to for one of the above conditions and is not still active when the blocking condition is removed, the
denied interrupt will not be serviced. In other words, the fact that the interrupt flag was once active but not
serviced is not remembered. Every polling cycle is new.
The processor acknowledges an interrupt request by executing a hardware-generated LCALL to the appropriate
servicing routine. In some cases it also clears the flag that generated the interrupt, and in other cases it doesn’t.
It never clears the interrupt flags of Timer2, Serial Port, SPI, TWSI, Keypad and USB. This has to be done in the
user’s firmware. It clears an external interrupt flag (IE0, IE1, IE2 or IE3) only if it was transition-activated. The
hardware-generated LCALL pushes the contents of the Program Counter onto the stack (but it does not save
the PSW) and reloads the PC with an Vector Address that depends on the source of the interrupt being
vectored to, as shown in Table 19-1.
Execution proceeds from that location until the RETI instruction is encountered. The RETI instruction informs
the processor that this interrupt routine is no longer in progress, then pops the top two bytes from the stack and
reloads the Program Counter. Execution of the interrupted program continues from where it left off.
Note that a simple RET instruction would also have returned execution to the interrupted program, but it would
have left the interrupt control system thinking the interrupt was still in progress.
Note that the starting addresses of consecutive interrupt service routines are only 8 bytes apart. That means if
consecutive interrupts are being used (IE0 and TF0, for example, or TF0 and IE1), and if the first interrupt
routine is more than 7 bytes long, then that routine will have to execute a jump to some other memory location
where the service routine can be completed without overlapping the starting address of the next interrupt routine
MEGAWIN
MG84FL54B Data sheet
53