mg84fl54 Megawin Technology, mg84fl54 Datasheet - Page 93

• Manufacturer Part Number: mg84fl54
• Description: Full-speed Usb Micro-controller
• Manufacturer: Megawin Technology

IEN (Interrupt Enable Register, Address=D9H, SYS_reset=xxxx-x00x, Read/Write)
Bit7~3: Reserved.
Bit2: EFSR-- Enable USB Reset/Suspend/Resume interrupt flag.
Bit1: EF-- Enable USB endpoint function interrupt Flag.
Bit0: Reserved.
UIE (USB Interrupt Enable Register, Address=DAH, SYS/USB_reset=00x0-x000, Read/Write)
Bit7: SOFIE-- Host SOF received Interrupt Enable.
If this bit is set, enables the Host SOF received interrupt. Default is cleared.
Bit6: ASOFIE-- ART SOF received Interrupt Enable.
If this bit is set, enables the ART SOF received interrupt. Default is cleared.
Bit5: Reserve.
Bit4: UTXIE2-- USB Endpoint 2 Transmit Interrupt Enable.
Bit3: Reserved.
Bit2: UTXIE1-- USB Endpoint 1 Transmit Interrupt Enable.
Bit1: URXIE0-- USB Endpoint 0 Receive Interrupt Enable.
Bit0: UTXIE0-- USB Endpoint 0 Transmit Interrupt Enable.
UIFLG (USB Interrupt Flag Register, Address=DBH, SYS/USB_reset=00x0-x000, Read/Write)
Bit7: SOFIF-- Host SOF received Interrupt Flag.
Bit6: ASOFIF-- ART SOF received Interrupt Flag.
Bit5: Reserved.
Bit4: UTXD2-- USB Transmit Done Flag for endpoint 2.
MEGAWIN
SOFIE
SOFIF
7
7
7
If this bit is set, enables USB reset/suspend/resume interrupts which are included in UPCON register. This
bit doesn't be reset USB_RESET. Default is cleared.
If this bit is set, enables global USB endpoint function interrupts which are included in UIFLG/UIFLG1
register. Transmit/receive done interrupt enable bit for USB function endpoints. This bit doesn't be reset by
USB_RESET. Default is cleared.
If this bit is set, enables the transmit done interrupt for USB endpoint 2 (UTXD2). Default is cleared.
If this bit is set, enables the transmit done interrupt for USB endpoint 1 (UTXD1). Default is cleared.
If this bit is set, enables the receive done interrupt for USB endpoint 0 (URXD0). Default is cleared.
If this bit is set, enables the transmit done interrupt for USB endpoint 0 (UTXD0). Default is cleared.
This bit is set by hardware when detected a host SOF. Firmware can read/write-clear on this bit. This bit is
cleared when firmware writes '1' to it.
This bit is set by hardware when detected an ART SOF. ART SOF is a synchronous signal with host SOF
that will be generated by hardware expecting to detect a host SOF, even if the real host SOF is missing or
corrupted. Firmware can read/write-clear on this bit. This bit is cleared when firmware writes '1' to it.
-
ASOFIE
ASOFIF
6
6
6
-
5
5
5
-
-
-
UTXIE2
UTXD2
4
4
4
-
MG84FL54B Data sheet
3
3
3
-
-
-
UTXIE1
UTXD1
EFSR
2
2
2
URXIE0
URXD0
EF
1
1
1
UTXIE0
UTXD0
0
0
0
-
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