mg84fl54 Megawin Technology, mg84fl54 Datasheet - Page 97

• Manufacturer Part Number: mg84fl54
• Description: Full-speed Usb Micro-controller
• Manufacturer: Megawin Technology

Bit4: RXFFRC-- Receive FIFO Read Complete.
Bit3~0: Reserved.
RXCNT (Receive FIFO Byte Count Register, Endpoint-Indexed, Address=E6H, SYS/USB_reset=x000-0000,
Read-only)
Bit6~0: RXBC[6:0]-- Receive Byte Count.
TXSTAT (Endpoint Transmit Status Register, Endpoint-Indexed, Address=F2H, SYS/USB_reset=0xxx-0xxx,
Read/Write)
Bit7: TXSEQ-- Transmit Endpoint Sequence Bit (read, conditional write).
Bit6~4: Reserved.
Bit3: TXSOVW-- Transmit Data Sequence Overwrite Bit.
Bit2~0: Reserved.
TXDAT (Transmit FIFO Data Register, Endpoint-Indexed, Address=F3H, SYS/USB_reset=xxxx-xxxx, Write-only)
Bit7~0: TXD[7:0]-- Transmit FIFO Data.
TXCON (Transmit FIFO Control Register, Endpoint-Indexed, Address=F4H, SYS/USB_reset=0xx0-xxxx, Write-
only)
Bit7: TXCLR-- Transmit FIFO Clear.
Bit6~5: Reserved.
Bit4: TXFFRC-- Transmit FIFO Write Complete.
Bit3~0: Reserved.
MEGAWIN
TXSEQ
TXCLR
TXD7
7
7
7
7
Set this bit to release the receive FIFO when data set read is complete. Hardware clears this bit after the
FIFO release operation has been finished. After this bit had been cleared to “0” by hardware, the FIFO
would be dedicated to USB transceiver to receive the incoming data in next OUT transaction.
Store the byte count for the data packet received in the receive FIFO specified by EPINDEX.
The bit will be transmitted in the next PID and toggled on a valid ACK handshake of an IN transaction. This
bit can be written by firmware if the TXOVW bit is set when written along with the new TXSEQ value.
Write '1' to this bit to allow the value of the TXSEQ bit to be overwritten. Writing a '0' to this bit has no
effect on TXSEQ. This bit always returns '0' when read.
Data to be transmitted in the FIFO specified by EPINDEX is written to this register.
Set this bit to flush the entire transmit FIFO. All FIFO statuses are reverted to their reset states. Hardware
clears this bit when the flush operation is completed.
Set this bit to release the transmit FIFO when data write is complete. Hardware clears this bit after the
FIFO release operation has been finished. Firmware should write this bit only after firmware finished
writing TXCNT register. After this bit had been cleared to “0” by hardware, the data in TXFIFO would be
sent by USB transceiver in next IN transaction.
-
RXBC6
TXD6
6
6
6
6
-
-
RXBC5
TXD5
5
5
5
5
-
-
TXFFRC
RXBC4
TXD4
4
4
4
4
-
MG84FL54B Data sheet
TXSOVW
RXBC3
TXD3
3
3
3
3
-
RXBC2
TXD2
2
2
2
2
-
-
RXBC1
TXD1
1
1
1
1
-
-
RXBC0
TXD0
0
0
0
0
-
-
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