mg84fl54 Megawin Technology, mg84fl54 Datasheet - Page 62

• Manufacturer Part Number: mg84fl54
• Description: Full-speed Usb Micro-controller
• Manufacturer: Megawin Technology

16. Serial Peripheral Interface (SPI)
The device provides a high-speed serial communication interface, the SPI interface. SPI is a full-duplex, high-
speed and synchronous communication bus with two operation modes: Master mode and Slave mode. Up to 4
Mbps can be supported in either Master or Slave mode under the 12MHz system clock. A specially designed
Transmit Holding Register (THR) improves the transmit performance compared to the conventional SPI.
Fig 16-1 SPI Block Diagram
The SPI interface has four pins: MISO (P2.6), MOSI (P2.5), SPICLK (P2.7) and /SS (P2.4):
• SPICLK, MOSI and MISO are typically tied together between two or more SPI devices. Data flows from master
to slave on the MOSI pin (Master Out / Slave In) and flows from slave to master on the MISO pin (Master In /
Slave Out). The SPICLK signal is output in the master mode and is input in the slave mode. If the SPI system is
disabled, i.e., SPEN (SPCTL.6) = 0, these pins function as normal I/O pins.
• /SS is the optional slave select pin. In a typical configuration, an SPI master asserts one of its port pins to
select one SPI device as the current slave. An SPI slave device uses its SS pin to determine whether it is
selected. But if SPEN (SPCTL.6) = 0 or SSIG (SPCTL.7) = 1, the /SS pin is ignored.
Note that even if the SPI is configured as a master (MSTR = 1), it can still be converted to a slave by driving the
/SS pin low (if SSIG = 0). Should this happen, the SPIF bit (SPSTAT.7) will be set. See Section "Mode change
on /SS-pin".
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SYSCLK
Clock Divider
16
48
12
24
96
4
8
6
SSIG
SPIF
Transmit Holding
Receive Data
Register
SPEN DORD MSTR
THRE
Buffer
MG84FL54B Data Sheet
SPI Control
Output Shift
Intput Shift
Register
Register
SYNCEN
CPOL
CKOD SSPOL SPR2
CPHA
I/O control
SPR1
SPR0
(SPICLK)
(MISO)
(MOSI)
SPCTL
SPSTAT
P2.6
P2.5
P2.7
P2.4
(SS)
MEGAWIN