mg84fl54 Megawin Technology, mg84fl54 Datasheet - Page 96

• Manufacturer Part Number: mg84fl54
• Description: Full-speed Usb Micro-controller
• Manufacturer: Megawin Technology

Table 19-3 Maximum Data Packet Size for USB Endpoint
RXSTAT (Endpoint Receive Status Register, Endpoint-Indexed, Address=E2H, SYS/USB_reset=0000-00xx,
Read/Write)
Bit7: RXSEQ-- Receive Endpoint Sequence Bit (read, conditional write).
Bit6: RXSETUP-- Received Setup Transaction.
Bit5: STOVW-- Start Overwrite Flag (read-only).
Bit4: EDOVW-- End Overwrite Flag.
Bit3: RXSOVW-- Receive Data Sequence Overwrite Bit.
Bit2: ISOOVW-- Isochronous receive data Overwrite Bit.
Bit1~0: Reserved.
RXDAT (Receive FIFO Data Register, Endpoint-Indexed, Address=E3H, SYS/USB_reset=xxxx-xxxx, Read-only)
Bit7~0: RXD[7:0]-- Receive FIFO Data.
RXCON (Receive FIFO Control Register, Endpoint-Indexed, Address=E4H, SYS/USB_reset=0xx0-xxxx, Write-
only)
Bit7: RXCLR-- Receive FIFO Clear.
Bit6~5: Reserved.
96
RXSEQ
RXCLR
Endpoint
RXD7
7
7
7
The bit will be toggled on completion of an ACK handshake in response to an OUT token. This bit can be
written by firmware if the RXOVW bit is set when written along with the new RXSEQ value.
This bit is set by hardware when a valid SETUP transaction has been received. Clear this bit upon
detection of a SETUP transaction or the firmware is ready to handle the data/status stage of control
transfer. Before firmware clear this bit, the device will response NAK packet in the handshake phase for
the following data/status stage of control transfer.
Set by hardware upon receipt of a SETUP token for the control endpoint to indicate that the receive FIFO
is being overwritten with new SETUP data. This bit is used only for control endpoints.
This flag is set by hardware during the handshake phase of a SETUP transaction. This bit is cleared by
firmware to read the FIFO data. This bit is only used for control endpoints.
Write '1' to this bit to allow the value of the RXSEQ bit to be overwritten. Writing a '0' to this bit has no
effect on RXSEQ. This bit always returns '0' when read.
This bit is set by hardware as a FIFO access conflict happen when firmware read the last data and USB
host send the next data in the same time. Firmware can use this bit to make sure whether the data had
been overwritten or not. When this bit is set, Firmware should write ‘0’ to clear this bit.
Receive FIFO data specified by EPINDEX is stored and read from this register.
Set this bit to flush the entire receive FIFO. All FIFO statuses are reverted to their reset states. Hardware
clears this bit when the flush operation is completed.
1
2
3
RXSETUP
RXD6
6
6
6
-
INT/BULK IN
TXDBM=0/1
64/64
64/32
64/64
STOVW
RXD5
5
5
5
-
RXFFRC
EDOVW
MG84FL54B Data Sheet
RXD4
INT/BULK OUT
4
4
4
RXDBM=0/1
64/32
N/A
N/A
Maximum Data Packet Size
RXSOVW
RXD3
3
3
3
-
ISOOVW
RXD2
2
2
2
-
TXDBM=0/1
ISO IN
64/32
64/64
N/A
RXD1
1
1
1
-
-
RXD0
0
0
0
-
-
RXDBM=0/1
ISO OUT
64/32
N/A
N/A
MEGAWIN