mg84fl54 Megawin Technology, mg84fl54 Datasheet - Page 65

• Manufacturer Part Number: mg84fl54
• Description: Full-speed Usb Micro-controller
• Manufacturer: Megawin Technology

16.2. Configuring the SPI
Table 16-1 SPI Master and Slave Selection
“X” means “don’t care”.
16.2.1. Additional Considerations for a Slave
When CPHA is 0, SSIG must be 0 and /SS pin must be negated and reasserted between each successive serial
byte transfer. Note the SPDAT register cannot be written while /SS pin is active (low), and the operation is
undefined if CPHA is 0 and SSIG is 1.
When CPHA is 1, SSIG may be 0 or 1. If SSIG=0, the /SS pin may remain active low between successive
transfers (can be tied low at all times). This format is sometimes preferred for use in systems having a single
fixed master and a single slave configuration.
16.2.2. Additional Considerations for a Master
In SPI, transfers are always initiated by the master. If the SPI is enabled (SPEN=1) and selected as master,
writing to the SPI data register (SPDAT) by the master starts the SPI clock generator and data transfer. The
data will start to appear on MOSI about one half SPI bit-time to one SPI bit-time after data is written to SPDAT.
Before starting the transfer, the master may select a slave by driving the /SS pin of the corresponding device
low. Data written to the SPDAT register of the master is shifted out of MOSI pin of the master to the MOSI pin of
the slave. And, at the same time the data in SPDAT register of the selected slave is shifted out on MISO pin to
the MISO pin of the master.
After shifting one byte, the SPI clock generator stops, setting the transfer completion flag (SPIF) and an interrupt
will be created if the SPI interrupt is enabled. The two shift registers in the master CPU and slave CPU can be
considered as one distributed 16-bit circular shift register. When data is shifted from the master to the slave,
data is also shifted in the opposite direction simultaneously. This means that during one shift cycle, data in the
master and the slave are interchanged.
(SPCTL.
MEGAWIN
SPEN
6)
0
1
1
1
1
1
1
(SPCTL.
SSIG
7)
X
0
0
0
0
1
1
/SS
-pin
X
X
X
0
1
0
1
(SPCTL.
MSTR
1
4)
X
0
0
1
0
1
0
(not selected)
SPI disabled
(selected)
(by mode
change)
(active)
Master
Master
Master
Mode
Salve
Slave
Slave
Slave
(idle)
MG84FL54B Data sheet
output
output
output
MISO
input
input
input
Hi-Z
-pin
output
output
MOSI
input
input
input
input
input
Hi-Z
-pin
SPICLK
output
output
input
input
input
input
input
Hi-Z
-pin
MSTR will be cleared to ‘0’ by
MOSI and SPICLK are push-
high impedance to avoid bus
contention when the Master
if /SS pin is driven low, and
MOSI and SPICLK are at
P2.4~P2.7 are used as
pull when the Master is
Mode change to slave
H/W automatically.
Selected as slave.
general port pins.
Not selected.
Remarks
active.
is idle.
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