mg84fl54 Megawin Technology, mg84fl54 Datasheet - Page 85

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mg84fl54

Manufacturer Part Number
mg84fl54
Description
Full-speed Usb Micro-controller
Manufacturer
Megawin Technology
Datasheet
18. One-Time-Enabled Watchdog Timer (WDT)
The WDT is intended as a recovery method in situations where the CPU may be subjected to firmware upset.
The WDT consists of a 15-bits free-running counter, an 8-bit prescaler and a control register (WDTCR). System
clock (SYSCLK) available for the WDT. The block diagram is shown below.
18.1. WDT Block Diagram
Fig 18-1 WDT Block Diagram
To enable the WDT, users must set ENW bit (WDTCR.5). When the WDT is enabled, the counter will increment
one by an interval of
bit (WDTCR.4) before WDT overflows. When WDT overflows, the CPU will reset itself and re-start.
Why the WDT is called “One-time Enabled”? It is because: Once the WDT is enabled by setting ENW bit, there
is no way to disable it except through power-on reset, which will clear the ENW bit. The WDTCR register will
keep the previous programmed value unchanged after hardware (RST-pin) reset, software reset and WDT reset.
For example, if the WDTCR is 0x2D, it still keeps at 0x2D rather than 0x00 after these resets. Only power-on
reset can initialize it to 0x00.
WDTCR (Address=E1H, Watch-Dog-Timer Control Register)
WRF: WDT reset flag.
When WDT overflows, this bit is set by H/W. It should be cleared by firmware.
ENW: Enable WDT.
Set to enable WDT.
Note:
CLRW: Clear WDT.
“Writing 1” to this bit will clear WDT.
Note:
WIDL: WDT in Idle mode.
Set this bit to let WDT keep counting while the CPU is in the idle mode.
PS2~PS1: Prescaler select.
See the following Table.
MEGAWIN
SYSCLK/12
IDLE
WRF
7
Once set, it can only be cleared by power-on reset.
It has no need to be cleared by “writing 0”.
WDTCR Register
6
-
WRF
(12 x Prescaler /
--
ENW
ENW
5
CLRW
SYSCLK). And now the user needs to clear it by writing “1” to the CLRW
CLRW
WIDL
4
MG84FL54B Data sheet
8-bits prescaler
PS2
1/256
1/128
1/64
1/32
1/16
1/8
1/4
1/2
PS1
WIDL
3
PS0
PS2
2
15-bits WDT
PS1
1
PS0
0
WDT Reset
85

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