nt1gt72u89d0bv Nanya Techology, nt1gt72u89d0bv Datasheet - Page 21

• Manufacturer Part Number: nt1gt72u89d0bv
• Description: Based On Ddr2-667/800 128mx8 1gb/2gb And 256mx4 2gb/4gb Sdram D-die
• Manufacturer: Nanya Techology

Symbol
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NT1GT72U89D0BV / NT2GT72U4PD0BV / NT4GT72U4ND0BV
NT2GT72U8PD0BV
1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72
PC2-5300 / PC3-6400
Registered DDR2 SDRAM DIMM
Operating, Standby, and Refresh Currents
I
Note: Module IDD was calculated from component IDD. It may different from the actual measurement.
REV 1.1
01/2009
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DD3PF
DD3PS
(T
DD4W
DD2P
DD2N
DD2Q
DD3N
DD4R
DD0
DD1
DD5
DD6
DD7
CASE
= 0 ° C ~ 85 ° C; V
Operating Current: One bank Active – Precharge; t
HIGH,
inputs are switching.
Operating Current: One bank; active/read/precharge; BL = 4; t
= 0mA; t
inputs are switching; Databus inputs are switching.
Precharge Power-Down Current: Other control and address inputs are stable, Data bus inputs are
floating.
Precharge Standby Current: All banks idle;
and address inputs are switching, data bus inputs are switching.
Precharge Quiet Standby Current: All banks idle;
control and address inputs are stable, Data bus inputs are floating.
Active Power-Down Current: All banks open; t
address inputs are STABLE, Data bus inputs are floating. MRS A12 bit is set to low (Fast
Power-down Exit).
Active Power-Down Current: All banks open; t
address inputs are STABLE, Data bus inputs are floating. MRS A12 bit is set to high (Slow
Power-down Exit).
Active Standby Current: All banks open; Continuous burst reads; BL=4; AL=0; CL=CL
t
Address inputs are switching; Data bus inputs are switching; I
Operating Current: Burst read: All banks open; Continuous burst reads; BL = 4; AL = 0; CL = CL
t
Address inputs are switching; Data bus inputs are switching.
Operating Current: Burst write: All banks open; Continuous burst writes; BL = 4; AL = 0; CL = CL
MIN
Address inputs are switching; Data bus inputs are switching.
Auto-Refresh Current: t
CS is HIGH between valid commands, other control and address inputs are switching, Data bus
inputs are switching.
Self-Refresh Current: CKE ≤ 0.2V; external clock off, CK and
inputs are floating, Data bus inputs are floating. RESET is LOW. I
up to TCASE of 85 º C max
All Bank Interleave Read Current: All banks are being interleaved at minimum t
t
0mA
RAS (MAX)
CK
RRD
; t
= t
using a burst length of 4. Control and address bus inputs are stable during deselects. I
CK
CK (MIN)
= t
RAS
CK (MIN)
; t
is HIGH between valid commands. Address and control inputs are switching; Data bus
; t
= t
RP
RAS
RAS (MIN).
= t
; t
= t
DDQ
RAS
RP (MIN)
RAS (MAX)
= t
= 1.8V
CKE is HIGH,
RAS (MAX)
RC
; t
= t
; t
CK
RFC (MIN)
RP
0.1V; V
= t
; t
= t
RP
CK (MIN)
RP (MIN)
= t
, Refresh command every t
DD
RP (MAX)
Parameter/Condition
= 1.8V
; CKE is HIGH, CS is HIGH between valid commands.
; CKE is HIGH, CS is HIGH between valid commands.
is HIGH between valid commands. Address and control
; CKE is HIGH, CS is HIGH between valid commands.
CK
CK
is HIGH; CKE is HIGH. t
= t
= t
0.1V, See AC Characteristics) [4GB, 2Ranks, 256Mx4 DDR2 SDRAMs]
CK
CK (MIN)
CK (MIN)
is HIGH; CKE is HIGH; t
= t
CK (MIN),
, CKE is LOW; Other control and
, CKE is LOW; Other control and
21
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
RC
OUT
RFC
t
RC
= t
at 0V; Other control and address
DD6
= t
= t
= 0mA
RC (MIN);
RFC (MIN)
RC (MIN),
current values are guaranteed
CK
= t
CL=2.5; t
t
interval, CKE is HIGH,
RAS
CK (MIN).
CK
RC
= t
= t
without violating
RAS (MIN),
CK (MIN)
Other control
CK
MIN
= t
; Other
CK (MIN);
; t
CKE is
OUT
RAS
=
=
I
OUT
MIN
;
PC2-5300
© NANYA TECHNOLOGY CORP.
(-3C)
3509
3311
2915
2321
1450
2717
3905
3608
4697
5192
658
777
697
PC2-6400
(-AD)
4004
3806
3317
2519
1529
4400
4103
5192
5786
3113
658
777
697
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA