nt1gt72u89d0bv Nanya Techology, nt1gt72u89d0bv Datasheet - Page 4

• Manufacturer Part Number: nt1gt72u89d0bv
• Description: Based On Ddr2-667/800 128mx8 1gb/2gb And 256mx4 2gb/4gb Sdram D-die
• Manufacturer: Nanya Techology

NT1GT72U89D0BV / NT2GT72U4PD0BV / NT4GT72U4ND0BV
NT2GT72U8PD0BV
1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72
PC2-5300 / PC3-6400
Registered DDR2 SDRAM DIMM
Input/Output Functional Description
REV 1.1
01/2009
A[13:11,10/AP,9:0]
DQS[17:0]
CKE[1:0]
ODT[1:0]
DQ[63:0]
V
V
Symbol
CB[7:0]
DM[8:0]
BA[2:0]
SA[2:0]
Par_In
,
DD,
V
V
SDA
CK0
SCL
DDSPD
[1:0]
DDQ
REF
[17:0]
V
0
SS
,
Supply
Supply
Supply
Supply
Type
OUT
I/O
I/O
I/O
I/O
I/O
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
Negative
Negative
Polarity
Positive
Positive
Active
Active
Active
Active
Active
Active
Edge
Edge
Edge
Edge
High
High
High
Low
Low
Low
-
-
-
-
-
-
-
-
-
-
Positive line of the differential pair of system clock inputs that drives input to the
on-DIMM PLL.
Negative line of the differential pair of system clock inputs that drives the input to the
on-DIMM PLL.
CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input
buffers and output drivers of the SDRAMs. Taking CKE LOW provides PRECHARGE
POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER
DOWN (row ACTIVE in any bank)
Enables the associated SDRAM command decoder when low and disables decoder
when high. When decoder is disabled, new commands are ignored and previous
operations continue. These input signals also disable all outputs (except CKE and ODT)
of the register(s) on the DIMM when both inputs are high. When both
register outputs (except CKE, ODT and Chip select) remain in the previous state. For
modules supporting 4 ranks,
register outputs.
When sampled at the positive rising edge of the clock,
operation to be executed by the SDRAM.
Reference voltage for SSTL-18 inputs
Isolated power supply for the DDR2 SDRAM output buffers to provide improved noise
immunity
On-Die Termination control signals
Selects which SDRAM bank is to be active.
During a Bank Activate command cycle, Address defines the row address.
During a Read or Write command cycle, Address defines the column address. In
addition to the column address, AP is used to invoke autoprecharge operation at the end
of the burst read or write cycle. If AP is high, autoprecharge is selected and BA0, BA1,
BA2 defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a
Precharge command cycle, AP is used in conjunction with BA0, BA1,BA2 to control
which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the
state of BA0 or BA1 or BA2. If AP is low, BA0 and BA1 and BA2 are used to define
which bank to precharge.
Data and Check Bit Input/Output pins.
Power and ground for the DDR2 SDRAM input buffers and core logic
Data strobe for input and output data
Data strobe for input and output data
Masks write data when high, issued concurrently with input data.
The
When low, all register outputs will be driven low and the PLL clocks to the DRAMs and
register(s) will be nset to low level (the PLL will remain synchronized with the input clock)
These signals are tied at the system planar to either V
serial SPD EEPROM address range.
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor
must be connected from the SDA bus line to V
pull-up.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be
connected from the SCL bus time to V
Serial EEPROM positive power supply (wired to a separate power pin at the connector
which supports from 1.7 Volt to 3.6 Volt (nominal 1.8 Volt, 2.5 Volt and 3.3 Volt)
operation.
Parity bit for the Address and Control bus. (1 for Odd, 0 for Even)
Parity error found in the Address and Control bus.
pin is connected to the
4
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
“
[2:3] operate similarly to
DD
Function
pin on the register and to the OE pin on the PLL.
to act as a pull-up.
DDSPD
on the system planar to act as a
SS
“
or V
[0:1] for a second set of
,
DDSPD
© NANYA TECHNOLOGY CORP.
,
to configure the
“
define the
[0:1]
are high, all