mt47h64m8b6-5e-it Micron Semiconductor Products, mt47h64m8b6-5e-it Datasheet - Page 102

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mt47h64m8b6-5e-it

Manufacturer Part Number
mt47h64m8b6-5e-it
Description
512mb X4, X8, X16 Ddr2 Sdram
Manufacturer
Micron Semiconductor Products
Datasheet
Figure 67:
PDF: 09005aef82f1e6e2/Source: 09005aef821aed36
DDR2_x4x8x16_Core2.fm - 512Mb DDR2: Rev. L; Core DDR2: Rev. C 4/08 EN
Bank address
DQS, DQS#
Command
Address
DQ 6
CK#
CKE
A10
DM
CK
NOP 1
Bank Write – with Auto Precharge
T0
Notes:
Bank x
ACT
RA
RA
T1
1. NOP commands are shown for ease of illustration; other commands may be valid at these
2. BL = 4 and AL = 0 in the case shown.
3. Enable auto precharge.
4. WR is programmed via MR9–MR11 and is calculated by dividing
5. Subsequent rising DQS signals must align to the clock within
6. DI n = data-in from column n; subsequent elements are applied in the programmed order.
7.
8.
times.
rounding up to the next integer value.
t
t
t CK
DSH is applicable during
DSS is applicable during
t RCD
NOP 1
T2
t CH
t CL
WRITE 2
Bank x
Col n
3
T3
WL ± t DQSS (NOM)
t
t
DQSS (MAX) and is referenced from CK T6 or T7.
DQSS (MIN) and is referenced from CK T5 or T6.
WL = 2
NOP 1
102
T4
t WPRE
t RAS
Micron Technology, Inc., reserves the right to change products or specifications without notice.
NOP 1
T5
DI
n
T5n
512Mb: x4, x8, x16 DDR2 SDRAM
t DQSL t DQSH t WPST
NOP 1
5
T6
T6n
Transitioning Data
NOP 1
t
DQSS.
T7
©2004 Micron Technology, Inc. All rights reserved.
t
WR (in ns) by
NOP 1
WR 4
T8
Operations
t
CK and
Don’t Care
NOP 1
T9
t RP

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