mt47h64m8b6-5e-it Micron Semiconductor Products, mt47h64m8b6-5e-it Datasheet - Page 56

• Manufacturer Part Number: mt47h64m8b6-5e-it
• Description: 512mb X4, X8, X16 Ddr2 Sdram
• Manufacturer: Micron Semiconductor Products

Table 31:
PDF: 09005aef82f1e6e2/Source: 09005aef821aed36
DDR2_x4x8x16_Core2.fm - 512Mb DDR2: Rev. L; Core DDR2: Rev. C 4/08 EN
(V/ns)
Slew
Rate
DQ
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
–100 –188 –100 –188 –100 –188
t
100
–13
–22
–34
–60
67
2.8 V/ns
DS
–5
Δ
0
DDR2-667/DDR2-800/DDR2-1066
All units are shown in picoseconds
–125
t
–14
–31
–54
–83
DH
63
42
Δ
0
Notes:
t
100
–13
–22
–34
–60
2.4 V/ns
67
–5
DS
Δ
0
1. For all input signals the total
2.
3.
4. Although the total setup time might be negative for slow slew rates (a valid input signal
5. For slew rates between the values listed in this table, the derating values may be obtained
6. These values are typically not subject to production test. They are verified by design and
7. Single-ended DQS requires special derating. The values in Table 32 on page 57 are the DQS
–125
t
–14
–31
–54
–83
DH
63
42
Δ
0
value to the derating value listed in Table 31.
t
of V
defined as the slew rate between the last crossing of V
V
the shaded “V
Figure 30 on page 59). If the actual signal is later than the nominal slew rate line anywhere
between shaded “V
from the AC level to DC level is used for the derating value (see Figure 31 on page 59).
t
ing of V
nal is defined as the slew rate between the last crossing of V
of V
shaded “DC level to V
Figure 32 on page 60). If the actual signal is earlier than the nominal slew rate line any-
where between the shaded “DC to V
actual signal from the DC level to V
on page 60).
will not have reached V
signal is still required to complete the transition and reach V
by linear interpolation.
characterization.
single-ended slew rate derating with DQS referenced at V
levels
trip points to DQs referenced to V
provides the V
not advised to operate DDR2-800 and DDR2-1066 devices with single-ended DQS; however
Table 32 on page 57 would be used with the base values.
DS nominal slew rate for a rising signal is defined as the slew rate between the last crossing
DH nominal slew rate for a rising signal is defined as the slew rate between the last cross-
IL
(
AC
t
100
–13
–22
–34
–60
REF
REF
67
2.0 V/ns
DS
–5
Δ
0
) MAX. If the actual signal is always earlier than the nominal slew rate line between
t
DS
(
(
DC
DC
IL
(
b
–125
) and the first crossing of V
DC
). If the actual signal is always later than the nominal slew rate line between the
t
–14
–31
–83
–54
and
DH
63
42
Δ
0
) MAX and the first crossing of V
REF
REF
t
DQS, DQS# Differential Slew Rate
DH
t
112
–10
–22
–48
–88
(
-based fully derated values for the DQ (
79
12
–1
1.8 V/ns
DS
Δ
7
DC
b
REF
. Converting the derated base values from DQs referenced to the AC/DC
) to AC region,” use the nominal slew rate for the derating value (see
t
REF
(
DS,
–113
–176
t
–19
–42
–71
DC
IH
DH
75
54
12
–2
Δ
(
DC
[
) to AC region,” the slew rate of a tangent line to the actual signal
AC
t
) region,” use the nominal slew rate for the derating value (see
DH Derating Values with Differential Strobe
]/V
56
t
124
t
–10
–36
–76
1.6 V/ns
DS
91
24
19
11
DS and
Δ
2
IL
[
AC
REF
REF
–101
–164
] at the time of the rising clock transition), a valid input
t
–30
–59
DH
87
66
24
10
–7
Δ
IH
REF
is listed in Table 33 on page 57. Table 33 on page 57
t
(
DH required is calculated by adding the data sheet
(
DC
Micron Technology, Inc., reserves the right to change products or specifications without notice.
AC
(
DC
) level is used for the derating value (see Figure 33
) MIN.
t
136
103
–24
–64
36
31
23
) region,” the slew rate of a tangent line to the
1.4 V/ns
DS
14
Δ
2
REF
512Mb: x4, x8, x16 DDR2 SDRAM
(
–152
t
t
DC
–47
–89
–18
DS nominal slew rate for a falling signal is
DH
99
78
36
22
Δ
5
).
t
DH nominal slew rate for a falling sig-
t
148
115
REF
–12
–52
1.2 V/ns
DS
48
43
35
26
14
Input Slew Rate Derating
Δ
t
REF
DS
(
DC
IH
a
and DQ referenced at the logic
–140
) and the first crossing of
IH
t
111
–35
–77
(
DH
and
90
48
34
17
–6
DC
Δ
(
AC
©2004 Micron Technology, Inc. All rights reserved.
) MIN and the first crossing
)/V
t
DH
t
160
127
–40
IL
60
55
47
26
1.0 V/ns
DS
38
Δ
0
(
a
AC
) for DDR2-667. It is
).
–128
t
123
102
–23
–65
DH
60
46
29
Δ
6
t
172
139
–28
0.8 V/ns
72
67
59
50
38
12
DS
Δ
–116
t
135
114
–11
–53
DH
72
58
41
18
Δ