mt47h64m8b6-5e-it Micron Semiconductor Products, mt47h64m8b6-5e-it Datasheet - Page 105

• Manufacturer Part Number: mt47h64m8b6-5e-it
• Description: 512mb X4, X8, X16 Ddr2 Sdram
• Manufacturer: Micron Semiconductor Products

REFRESH
Figure 70:
Bank address
PDF: 09005aef82f1e6e2/Source: 09005aef821aed36
DDR2_x4x8x16_Core2.fm - 512Mb DDR2: Rev. L; Core DDR2: Rev. C 4/08 EN
DQS, DQS# 4
Command
Address
DM 4
DQ 4
CK#
CKE
A10
CK
NOP 1
Refresh Mode
T0
Notes:
One bank
All banks
Bank(s) 3
PRE
T1
The commercial temperature DDR2 SDRAM requires REFRESH cycles at an average
interval of 7.8125µs (MAX) and all rows in all banks must be refreshed at least once every
64ms. The refresh period begins when the REFRESH command is registered and ends
t
+85°C.
1. NOP commands are shown for ease of illustration; other valid commands may be possible at
2. The second REFRESH is not required and is only shown as an example of two back-to-back
3. “Don’t Care” if A10 is HIGH at this point; A10 must be HIGH if more than one bank is active
4. DM, DQ, and DQS signals are all “Don’t Care”/High-Z for operations shown.
RFC (MIN) later. The average interval must be reduced to 3.9µs (MAX) when T
these times. CKE must be active during clock positive transitions.
REFRESH commands.
(must precharge all active banks).
t CK
NOP 1
T2
t CH
t RP
t CL
NOP 1
T3
105
REF
T4
t RFC (MIN)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
NOP 1
Ta0
512Mb: x4, x8, x16 DDR2 SDRAM
Ta1
REF 2
Indicates A Break in
Time Scale
NOP 1
Tb0
©2004 Micron Technology, Inc. All rights reserved.
t RFC 2
NOP 1
Tb1
Operations
C
Don’t Care
exceeds
Tb2
ACT
RA
RA
BA