mt47h64m8b6-5e-it Micron Semiconductor Products, mt47h64m8b6-5e-it Datasheet - Page 114
mt47h64m8b6-5e-it
Manufacturer Part Number
mt47h64m8b6-5e-it
Description
512mb X4, X8, X16 Ddr2 Sdram
Manufacturer
Micron Semiconductor Products
Datasheet
1.MT47H64M8B6-5E-IT.pdf
(122 pages)
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Figure 81:
PDF: 09005aef82f1e6e2/Source: 09005aef821aed36
DDR2_x4x8x16_Core2.fm - 512Mb DDR2: Rev. L; Core DDR2: Rev. C 4/08 EN
DQS, DQS#
Command
Address
ODT
CK#
CKE
DM
DQ
CK
High-Z
High-Z
Valid 4
Valid
T0
Input Clock Frequency Change During Precharge Power-Down Mode
t CH
power-down mode
t CK
Notes:
Enter precharge
t CL
Previous clock frequency
NOP
T1
new stable clocks must be provided to the device before precharge power-down may be
exited, and DLL must be reset via MR after precharge power-down exit. Depending on
the new clock frequency, additional LM commands might be required to adjust the CL,
WR, AL, and so forth. settings to account for the frequency change. Depending on the
new clock frequency, an additional LM command might be required to appropriately set
the WR MR9, MR10, MR11. During the DLL relock period of 200 cycles, ODT must
remain off. After the DLL lock time, the DRAM is ready to operate with a new clock
frequency.
1. A minimum of 2 ×
2. When the new clock frequency has changed and is stable, a minimum of 1 ×
3. Minimum CKE HIGH time is
4. If this command is a PRECHARGE (or if the device is already in the idle state), then the
2 x t CK (MIN) 1
clock frequencies.
prior to exiting precharge power-down.
requires a minimum of three clock cycles of registration.
power-down mode shown is precharge power-down, which is required prior to the clock
frequency change.
T2
t CKE (MIN) 3
T3
t
Frequency
CK is required after entering precharge power-down prior to changing
change
Ta0
t
114
1 x t CK (MIN) 2
CKE = 3 ×
t CH
power-down mode
t CK
Exit precharge
t CL
NOP
Ta1
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
CK. Minimum CKE LOW time is
New clock frequency
512Mb: x4, x8, x16 DDR2 SDRAM
NOP
Ta2
t XP
t CKE (MIN) 3
DLL RESET
Ta3
Indicates A Break in
Time Scale
LM
©2004 Micron Technology, Inc. All rights reserved.
200 x t CK
t
NOP
Ta4
CKE = 3 ×
Operations
t
CK is required
t
Don’t Care
CK. This
Valid
Valid
Tb0
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