mt47h64m8b6-5e-it Micron Semiconductor Products, mt47h64m8b6-5e-it Datasheet - Page 82

• Manufacturer Part Number: mt47h64m8b6-5e-it
• Description: 512mb X4, X8, X16 Ddr2 Sdram
• Manufacturer: Micron Semiconductor Products

Extended Mode Register 3 (EMR 3)
Figure 45:
ACTIVATE
PDF: 09005aef82f1e6e2/Source: 09005aef821aed36
DDR2_x4x8x16_Core2.fm - 512Mb DDR2: Rev. L; Core DDR2: Rev. C 4/08 EN
Extended Mode Register 3 (EMR3) Definition
Notes:
The extended mode register 3 (EMR3) controls functions beyond those controlled by the
mode register. Currently all bits in EMR3 are reserved, as shown in Figure 45 on page 82.
The EMR3 is programmed via the LM command and will retain the stored information
until it is programmed again or until the device loses power. Reprogramming the EMR
will not alter the contents of the memory array, provided it is performed correctly.
EMR3 must be loaded when all banks are idle and no bursts are in progress, and the
controller must wait the specified time
tion. Violating either of these requirements could result in an unspecified operation.
1. E16 (BA2) is only applicable for densities >1Gb, is reserved for future use, and must be pro-
2. Mode bits (En) with corresponding address balls (An) greater than E12 (A12) are reserved
Before any READ or WRITE commands can be issued to a bank within the DDR2
SDRAM, a row in that bank must be opened (activated), even when additive latency is
used. This is accomplished via the ACTIVATE command, which selects both the bank
and the row to be activated.
After a row is opened with an ACTIVATE command, a READ or WRITE command may be
issued to that row subject to the
the clock period and rounded up to the next whole number to determine the earliest
clock edge after the ACTIVATE command on which a READ or WRITE command can be
entered. The same procedure is used to convert other specification limits from time
units to clock cycles. For example, a
clock (
page 83, which covers any case where 5 <
case for
E15
BA2
16
0
0
0
1
1
grammed to “0.”
for future use and must be programmed to “0.”
1
E14
BA1
15
0
1
0
1
MRS
t
CK = 3.75ns) results in 5.3 clocks, rounded up to 6. This is shown in Figure 46 on
BA0
14
Extended mode register (EMR2)
Extended mode register (EMR3)
Extended mode register (EMR)
t
RRD where 2 <
0
n
An
Mode register (MR)
Mode Register Set
2
0
12
A12 A11
0
11
0
10
A10
0
9
A9
t
0
RRD (MIN)/
8
A8
0
7
A7 A6 A5 A4 A3
82
0
6
t
RCD specification.
0
5
0
t
4
RCD (MIN) specification of 20ns with a 266 MHz
t
CK ≤ 3.
0
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
3
MRD before initiating any subsequent opera-
0
t
2
RCD (MIN)/
A2 A1 A0
0
1
512Mb: x4, x8, x16 DDR2 SDRAM
0
0
Address bus
Extended mode
register (Ex)
t
RCD (MIN) should be divided by
t
CK ≤ 6. Figure 46 also shows the
©2004 Micron Technology, Inc. All rights reserved.
Operations