adf4196 Analog Devices, Inc., adf4196 Datasheet - Page 15

• Manufacturer Part Number: adf4196
• Description: Low Phase Noise, Fast Settling, 6 Ghz Pll Frequency Synthesizer
• Manufacturer: Analog Devices, Inc.

Data Sheet
FRAC/INT REGISTER (R0) LATCH MAP
R0, the FRAC/INT register, is used to program the synthesizer
output frequency. On the PFD cycle following a write to R0,
the N divider section is updated with the new INT and FRAC
values, and the PLL automatically enters fast lock mode. The
charge pump current is increased to its maximum value and
remains at this value until the I
and the SW1, SW2, and SW3 switches close and remain closed
until the SW1/SW2 and SW3 timeout counters time out.
After all the registers are programmed during the initialization
sequence (see Table 9), a new channel can be programmed
by performing a write to R0. However, as described in the
Programming the
to program the R1 and R2 register settings on a channel-by-
channel basis. These settings are double buffered by the write to
Register R0. This means that, although the data is loaded through
the serial interface on the respective R1 and R2 write cycles, the
synthesizer is not updated with their data until the next write to
Register R0.
DB23
N9
DB22
N8
N9
0
.
.
.
1
DB21
N7
N8
0
.
.
.
1
9-BIT RF INT VALUE
DB20
ADF4196
N6
DB19
N5
N7
0
.
.
.
1
section, it may also be desirable
DB18
N4
CP
timeout counter times out;
N6
0
.
.
.
1
DB17
N3
DB16
N5
1
.
.
.
1
N2
F12
0
0
0
0
.
.
.
1
1
1
1
DB15
N1
N4
1
.
.
.
1
DB14
F12
F11
0
0
0
0
.
.
.
1
1
1
1
Figure 29. Bit Map for Register R0
N3
0
.
.
.
1
DB13
F11
Rev. B | Page 15 of 28
F10
0
0
0
0
.
.
.
1
1
1
1
DB12
F10
N2
1
.
.
.
1
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
DB11
F9
Control Bits
To select R0, the FRAC/INT register, the three LSBs (C3, C2,
and C1) should be set to 0, 0, 0.
9-Bit RF INT Value
Bits[DB23:DB15] set the INT value, which determines the
integer part of the feedback division factor. All integer values
from 26 to 511 are allowed (see the Worked Example section).
12-Bit RF FRAC Value
Bits[DB14:DB3] set the numerator of the fraction that is input
to the Σ-Δ modulator. This fraction, along with INT, specifies
the new frequency channel that the synthesizer locks to, as shown
in the Worked Example section. FRAC values from 0 to MOD − 1
cover channels over a frequency range that is equal to the PFD
reference frequency.
N1
0
.
.
.
1
DB10
F8
12-BIT RF FRAC VALUE
F3
0
0
0
0
.
.
.
1
1
1
1
DB9
F7
INTEGER VALUE (INT)
26
.
.
.
511
DB8
F6
F2
0
0
1
1
.
.
.
0
0
1
1
DB7
F5
F1
0
1
0
1
.
.
.
0
1
0
1
DB6
F4
DB5
0 ≤ FRAC < MOD
FRACTIONAL VALUE (FRAC)
0
1
2
3
.
.
.
4092
4093
4094
4095
F3
DB4
F2
DB3
F1
C3 (0)
DB2
ADF4196
CONTROL
C2 (0)
BITS
DB1
C1 (0)
DB0