adf4196 Analog Devices, Inc., adf4196 Datasheet - Page 21

• Manufacturer Part Number: adf4196
• Description: Low Phase Noise, Fast Settling, 6 Ghz Pll Frequency Synthesizer
• Manufacturer: Analog Devices, Inc.

Data Sheet
MUX REGISTER (R6) LATCH MAP AND TRUTH TABLE
R6, the mux register, is used to program MUX
Σ-Δ and lock detect modes.
Control Bits
Register R6 is selected with C3, C2, and C1 set to 1, 1, 0.
Σ-Δ and Lock Detect Modes
Bit DB15 to Bit DB12 are used to reconfigure certain PLL
operating modes. In the initialization sequence after power is
applied to the chip, the four bits must first be programmed to
all zeros. This initializes the PLL to a known state with dither
off in the Σ-Δ modulator and a 3 ns PFD error threshold in the
lock detect circuit.
To turn on dither in the Σ-Δ modulator, an additional write should
be made to Register R6 to program Bits[DB15:DB12] = 0011.
However, for lowest noise operation, it is best to leave dither off.
To change the lock detect threshold from 3 ns to 10 ns, perform
a separate write to R6 to program Bits[DB15:DB12] = 1001.
This separate write is needed for reliable lock detect operation
when the RF frequency is <2 GHz.
A write to R6 that programs Bits[DB15:DB12] = 0000 returns
operation to the default state with both dither off and a 3 ns
lock detect threshold.
DB15
M13
0
0
1
M13
LOCK DETECT MODES
ALL OTHER STATES
SIGMA-DELTA
DB14
M12
M12
0
0
0
AND
DB13
M11
M11
0
1
0
DB12
M10
M10
0
1
1
DB11
Figure 35. Bit Map and MUX
0
OUT
SIGMA-DELTA MODES
INIT STATE, DITHER OFF,
3ns LOCK DETECT THRESHOLD
DITHER ON
10ns LOCK DETECT THRESHOLD
RESERVED
, as well as
DB10
0
RESERVED
DB9
0
Rev. B | Page 21 of 28
DB8
0
DB7
OUT
1
Truth Table for Register R6
DB6
Reserved Bits
For normal operation, the reserved bits (Bits[DB11:DB7]) must
be set to 00001.
MUX
These bits control the on-chip multiplexer, Pin 16 (see Figure 35
for the truth table). This pin is useful for diagnosis because it
allows the user to look at various internal points of the chip,
such as the R divider and the INT divider outputs.
In addition, it is possible to monitor the programmed timeout
counter intervals on MUX
counter is programmed to 65 (with a 26 MHz PFD), then
following the next write to R0, a pulse width of 10 µs is
observed on the MUX
Digital lock detect is available via the MUX
M4
M4
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
DB5
OUT
M3
MUX
M3
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Modes
OUT
M2
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
DB4
M2
M1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DB3
M1
MUX
3-STATE
DIGITAL LOCK DETECT
N DIVIDER OUTPUT
LOGIC HIGH
R DIVIDER OUTPUT
RESERVED
SERIAL DATA OUTPUT
LOGIC LOW
R DIVIDER/2 OUTPUT
N DIVIDER/2 OUTPUT
RESERVED
RESERVED
I
SW1/SW2 TIMEOUT SIGNAL
SW3 TIMEOUT SIGNAL
RESERVED
CP
C3 (1)
TIMEOUT SIGNAL
OUT
DB2
OUT
pin.
CONTROL
OUT
C2 (1)
BITS
DB1
. For example, if the I
C1 (0)
DB0
OUT
pin.
ADF4196
CP
timeout