adf4196 Analog Devices, Inc., adf4196 Datasheet - Page 22

• Manufacturer Part Number: adf4196
• Description: Low Phase Noise, Fast Settling, 6 Ghz Pll Frequency Synthesizer
• Manufacturer: Analog Devices, Inc.

ADF4196
PROGRAMMING THE
The
step or resolution that is a fraction of the input reference fre-
quency. For a given input reference frequency and a desired
output frequency step, the first choice to make is the PFD
reference frequency and the MOD value. After these are chosen,
the desired output frequency channels are set by programming
the INT and FRAC values.
WORKED EXAMPLE
In this example of a GSM900 Rx system, the RF output frequencies
must be generated with channel steps of 200 kHz. A reference
frequency input (REF
setting that determines the PFD reference is shown in Equation 3.
where:
REF
D is the doubler enable bit (0 or 1).
R is the 4-bit R counter code (1 to 15).
T is the REF/2 bit (0 or 1).
The maximum PFD reference frequency of 26 MHz is chosen,
and the following settings are programmed to give an R divider
value of 4:
•
•
•
Next, the modulus is chosen to allow fractional steps of 200 kHz:
When the channel step is defined, Equation 5 shows how output
frequency channels are programmed.
where:
RF
INT is the integer part of the division.
FRAC is the numerator part of the fractional division.
MOD is the modulus or denominator part of the fractional
division.
Thus, the frequency channel at 962.4 MHz is synthesized by
programming the following values: INT = 37 and FRAC = 2.
SPUR MECHANISMS
The following sections describe the three different spur
mechanisms that arise with a fractional-N synthesizer and how
the
Fractional Spurs
The fractional interpolator in the
modulator (SDM) with a modulus MOD that is programmable
to any integer value from 13 to 4095. If dither is enabled, the
OUT
ADF4196
IN
ADF4196
f
Doubler enable = 0
R = 2
REF/2 = 1
MOD = 26 MHz/200 kHz = 130
RF
PFD
is the input reference frequency.
is the desired RF output frequency.
OUT
= REF
= [INT + (FRAC/MOD)] × f
can best be programmed to minimize them.
can synthesize output frequencies with a channel
IN
× [(1 + D)/(R × (1 + T))]
IN
) of 104 MHz is available. The R divider
ADF4196
ADF4196
PFD
is a third-order, Σ-Δ
Rev. B | Page 22 of 28
(3)
(4)
(5)
minimum allowed value of MOD is 50. The SDM is clocked at
the PFD reference rate (f
to be synthesized at a channel step resolution of f
With dither turned off, the quantization noise from the Σ-Δ
modulator appears as fractional spurs. The interval between spurs
is f
the digital Σ-Δ modulator. For the third-order modulator used
in the ADF4196, the repeat length depends on the value of
MOD, as shown in Table 8.
Table 8. Fractional Spurs with Dither Off
Condition (Dither Off)
MOD Is Divisible by 2 but Not by 3
MOD Is Divisible by 3 but Not by 2
MOD Is Divisible by 6
All Other Divisors
With dither enabled, the repeat length is extended to 2
regardless of the value of MOD, which makes the quantization
error spectrum look like broadband noise. This can degrade the
in-band phase noise at the PLL output by as much as 10 dB.
Therefore, for lowest noise, dither off is a better choice, particularly
when the final loop bandwidth is low enough to attenuate even
the lowest frequency fractional spur. The wide loop bandwidth
range that is available with the
in most applications.
Integer Boundary Spurs
Another mechanism for fractional spur creation involves
interactions between the RF VCO frequency and the reference
frequency. When these frequencies are not integer related
(which is the purpose of a fractional-N synthesizer), spur
sidebands appear on the VCO output spectrum at an offset
frequency that corresponds to the beat note or difference
frequency between an integer multiple of the reference and
the VCO frequency.
These spurs are attenuated by the loop filter and are more
noticeable on channels that are close to integer multiples of the
reference, where the difference frequency can be inside the loop
bandwidth (thus, the name integer boundary spurs).
The 8:1 loop bandwidth switching ratio of the
it possible to attenuate all spurs to sufficiently low levels for most
applications. The final loop bandwidth can be chosen to ensure
that all spurs are far enough out of band and meet the lock time
requirements with the 8× bandwidth boost.
The programmable modulus and R divider of the
also be used to avoid integer boundary channels. This option is
described in the Avoiding Integer Boundary Channels section.
PFD
/L, where L is the repeat length of the code sequence in
PFD
), which allows PLL output frequencies
ADF4196
Repeat
Length
2 × MOD
3 × MOD
6 × MOD
MOD
allows the use of dither
ADF4196
Data Sheet
PFD
Spur Interval
Channel step/2
Channel step/3
Channel step/6
Channel step
ADF4196
/MOD.
21
cycles,
makes
can