adf4196 Analog Devices, Inc., adf4196 Datasheet - Page 19

• Manufacturer Part Number: adf4196
• Description: Low Phase Noise, Fast Settling, 6 Ghz Pll Frequency Synthesizer
• Manufacturer: Analog Devices, Inc.

Data Sheet
CHARGE PUMP REGISTER (R4) LATCH MAP
R4, the charge pump register, is used for programming the timers
for loop filter switches. These switches help maintain the stability
of the loop filter after boosting the charge pump current.
Control Bits
Register R4 is selected with C3, C2, and C1 (Bits[DB2:DB0]) set
to 1, 0, 0.
Reserved Bits
For normal operation, set the DB23 to DB14 reserved bits to
a hexadecimal code of 0x001.
9-Bit Timeout Counter
These bits are used to program the fast lock timeout counters.
The counters are clocked at one-quarter the PFD reference
frequency; therefore, their time delay scales with the PFD
frequency according to the following equation:
For example, if 35 is loaded with timer select = 00, with
a 13 MHz PFD, SW1 and SW2 switch after the following:
DB23
0
Delay(s) = (Timeout Counter Value × 4)/(PFD Frequency)
(35 × 4)/13 MHz = 10.8 µs
DB22
0
DB21
0
DB20
0
DB19
RESERVED
0
DB18
0
DB17
0
DB16
0
DB15
0
C9
0
0
0
0
.
.
.
1
1
1
1
DB14
1
Figure 33. Bit Map for Register R4
C8
0
0
0
0
.
.
.
1
1
1
1
DB13
C9
Rev. B | Page 19 of 28
C7
0
0
0
0
.
.
.
1
1
1
1
DB12
C8
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
DB11
C7
9-BIT TIMEOUT COUNTER
Timer Select
The two timer select bits select the timeout counter that is to
be programmed. Note that setting up the
operation requires setup of these three timeout counters: I
SW1/SW2, and SW3. Therefore, three writes to this register
are required in the initialization sequence. Table 7 shows
example values for a GSM Tx synthesizer with a 60 kHz final
loop bandwidth. See the Applications Information section for
more information.
Table 7. Recommended Values for a GSM Tx LO
Timer
Select
10
01
00
On each write to R0, the timeout counters start. Switch SW3 closes
until the SW3 counter times out. Similarly, the SW1 and SW2
switches close until the SW1/SW2 counter times out. When the
I
from 64× to 1× in six binary steps. It is recommended that the
SW1/SW2 and SW3 timeout counter values be set equal to the
I
Table 7.
DB10
CP
CP
C6
C3
0
0
0
0
.
.
.
1
1
1
1
counter times out, the charge pump current is ramped down
timeout counter value plus 7, as in the example shown in
DB9
C5
C2
0
0
1
1
.
.
.
0
0
1
1
DB8
C4
C1
0
1
0
1
.
.
.
0
1
0
1
Timeout
Counter
I
SW3
SW1/SW2
CP
DB7
C3
TIMEOUT COUNTER
0
1
2
3
.
.
.
508
509
510
511
DB6
C2
F2
0
0
1
1
F1
0
1
0
1
DB5
C1
TIMER SELECT
SW1/SW2
SW3
I
NOT USED
CP
Value
28
35
35
DB4
F2
SELECT
TIMER
xPFD CYCLES
0
4
8
12
.
.
.
2032
2036
2040
2044
DB3
F1
ADF4196
1
DELAY WITH 26MHz PFD
C3 (1)
Time (µs) with
PFD = 13 MHz
8.6
10.8
10.8
DB2
CONTROL
ADF4196
C2 (0)
BITS
DB1
for correct
DELAY µs
0
0.15
0.30
0.46
.
.
.
78.15
78.30
78.46
78.61
C1 (0)
DB0
CP
1
,