adf4196 Analog Devices, Inc., adf4196 Datasheet - Page 18

• Manufacturer Part Number: adf4196
• Description: Low Phase Noise, Fast Settling, 6 Ghz Pll Frequency Synthesizer
• Manufacturer: Analog Devices, Inc.

ADF4196
FUNCTION REGISTER (R3) LATCH MAP
R3, the function register, needs to be programmed only during
the initialization sequence (see Table 9).
Control Bits
Register R3 is selected with C3, C2, and C1 set to 0, 1, 1.
CPO GND
When the CPO GND bit is low, the charge pump outputs are
internally pulled to ground. This is invoked during the initiali-
zation sequence to discharge the loop filter capacitors. For
normal operation, this bit should be set to 1.
DB15
0
DB14
0
DB13
0
DB12
0
DB11
RESERVED
0
DB10
0
Figure 32. Bit Map for Register R3
DB9
0
Rev. B | Page 18 of 28
DB8
0
DB7
0
PFD Polarity
Set the PFD polarity bit to 1 for positive polarity, and set it to 0
for negative polarity.
Reserved Bits
Program the DB15 to DB6 reserved bits to a hexadecimal code of
0x001, and set the DB4 reserved bit to 1.
DB6
1
DB5
F3
F3
0
1
CPO GND
CPO/CPO GND
NORMAL
DB4
1
DB3
F1
F1
0
1
PFD POLARITY
NEGATIVE
POSITIVE
C3 (0)
DB2
CONTROL
C2 (1)
BITS
DB1
C1 (1)
DB0
Data Sheet