adf4196 Analog Devices, Inc., adf4196 Datasheet - Page 17

• Manufacturer Part Number: adf4196
• Description: Low Phase Noise, Fast Settling, 6 Ghz Pll Frequency Synthesizer
• Manufacturer: Analog Devices, Inc.

Data Sheet
PHASE REGISTER (R2) BIT LATCH MAP
R2, the phase register, is used to program the phase of the VCO
output signal.
Control Bits
Register R2 is selected with C3, C2, and C1 set to 0, 1, 0.
12-Bit Phase
The 12-bit phase word sets the seed value of the Σ-Δ modulator.
It can be programmed to any integer value from 0 to MOD, where
MOD is the modulus value that is programmed in Register R1,
Bits[DB14:DB3]. As the phase word is swept from 0 to MOD,
the phase of the VCO output sweeps over a 360° range in steps
of 360°/MOD.
Note that the phase bits are double buffered; they do not take
effect until the load enable of the next write to R0 (the FRAC/INT
register). Thus, to change the phase of the VCO output frequency,
it is necessary to rewrite the INT and FRAC values to Register R0
following the write to Register R2.
1
0 ≤ PHASE VALUE < MOD
DB15
0
DB14
P12
DB13
P11
P12
0
0
0
.
.
.
1
1
1
1
DB12
P10
P11
0
0
0
.
.
.
1
1
1
1
DB11
P9
P10
0
0
0
.
.
.
1
1
1
1
DB10
P8
Figure 31. Bit Map for Register R2
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
12-BIT PHASE
DB9
P7
Rev. B | Page 17 of 28
DB8
P3
0
0
0
.
.
.
1
1
1
1
P6
DB7
P5
P2
0
0
1
.
.
.
0
0
1
1
The output of a fractional-N PLL can settle to any one of the
MOD possible phase offsets with respect to the reference, where
MOD is the fractional modulus.
To keep the output at the same phase offset with respect to the
reference, each time that particular output frequency is pro-
grammed, the interval between writes to Register R0 must be an
integer multiple of MOD reference cycles.
To keep the outputs of two ADF4196-based synthesizers phase
coherent with each other (but not necessarily with the reference
they have in common), the write to Register R0 on both chips
must be performed during the same reference cycle. In this
case, the interval between the R0 writes does not need to be
an integer multiple of MOD cycles.
Reserved Bit
Set the reserved bit, DB15, to 0.
DB6
P4
P1
0
1
0
.
.
.
0
1
0
1
DB5
P3
PHASE VALUE
0
1
2
.
.
.
4092
4093
4094
4095
DB4
P2
DB3
P1
1
C3 (0)
DB2
CONTROL
C2 (1)
BITS
DB1
C1 (0)
DB0
ADF4196