adf4196 Analog Devices, Inc., adf4196 Datasheet - Page 16

• Manufacturer Part Number: adf4196
• Description: Low Phase Noise, Fast Settling, 6 Ghz Pll Frequency Synthesizer
• Manufacturer: Analog Devices, Inc.

ADF4196
MOD/R REGISTER (R1) LATCH MAP
R1, the MOD/R register, sets the PFD reference frequency and
the channel step size, which is determined by the PFD frequency
divided by the fractional modulus. Note that the 12-bit modulus,
the 4-bit RF R counter, the doubler enable bits, REF/2, and
CP ADJ are double buffered. They do not take effect until the
next write to R0 (the FRAC/INT register) is complete.
Control Bits
Register R1 is selected with C3, C2, and C1 set to 0, 0, 1.
CP ADJ
When the CP ADJ bit is set to 1, the charge pump current is
scaled up 25% from its nominal value on the next write to R0.
When this bit is set to 0, the charge pump current remains at its
nominal value on the next write to R0. See the Programming
the
can be used.
REF/2
Setting the REF/2 bit to 1 inserts a divide-by-2 toggle flip-flop
between the R counter and the PFD, which extends the maximum
REF
Reserved Bit
The reserved bit, DB21, must be set to 0.
DB23
F5
0
1
F5
ADF4196
F4
0
1
CP ADJ
NOMINAL
ADJUSTED
IN
input rate.
DB22
REF/2
DISABLED
ENABLED
F4
F2
0
1
PRESCALER
4/5
8/9
DB21
0
section for more information on how this feature
DB20
F2
DB19
F1
F1
0
1
DOUBLER ENABLE
DOUBLER DISABLED
DOUBLER ENABLED
DB18
R4
DB17
R COUNTER
R3
4-BIT RF
DB16
R4
0
0
0
0
.
.
.
1
1
1
1
R2
DB15
R3
0
0
0
1
.
.
.
1
1
1
1
R1
DB14
M12
M12
0
0
0
.
.
.
1
1
1
1
R2
0
1
1
0
.
.
.
0
0
1
1
Figure 30. Bit Map for Register R1
DB13
M11
M11
0
0
0
.
.
.
1
1
1
1
Rev. B | Page 16 of 28
R1
1
0
1
0
.
.
.
0
1
0
1
DB12
M10
M10
0
0
0
.
.
.
1
1
1
1
RF R COUNTER DIVIDE RATIO
1
2
3
4
.
.
.
12
13
14
15
DB11
M9
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
Prescaler (P/P + 1)
The dual-modulus prescaler (P/P + 1), along with INT, FRAC,
and MOD, determine the overall division ratio from RF
PFD input. Operating at CML levels, it takes the clock from the
RF input stage and divides it down for the counters. It is based on
a synchronous 4/5 core. When set to 4/5, the maximum RF
frequency allowed is 3 GHz. Therefore, when operating the
ADF4196
prescaler limits the INT value. If P = 4/5, then N
If P = 8/9, N
Doubler Enable
Setting the doubler enabler bit to 1 inserts a frequency doubler
between REF
bypasses the doubler.
4-Bit RF R Counter
The 4-bit RF R counter allows the REF
down to produce the reference clock to the PFD. All integer
values from 1 to 15 are allowed (see the Worked Example section).
12-Bit Modulus
For a given PFD reference frequency, the fractional denominator
or modulus sets the channel step resolution at the RF output. All
integer values from 13 to 4095 are allowed. See the Programming
the
selecting the value of MOD.
DB10
M8
ADF4196
12-BIT MODULUS
M3
1
1
1
.
.
.
1
1
1
1
DB9
M7
above 3 GHz, the prescaler must be set to 8/9. The
MIN
IN
DB8
section for a Worked Example and guidelines for
M2
0
1
1
.
.
.
0
0
1
1
M6
and the 4-bit RF R counter. Setting this bit to 0
= 80.
DB7
M5
M1
1
0
1
.
.
.
0
1
0
1
DB6
M4
INTERPOLATOR MODULUS VALUE (MOD)
13
14
15
.
.
.
4092
4093
4094
4095
DB5
M3
DB4
M2
IN
frequency to be divided
DB3
M1
Data Sheet
C3 (0)
DB2
MIN
CONTROL
= 26.
C2 (0)
BITS
DB1
IN
to the
C1 (1)
DB0