adf4196 Analog Devices, Inc., adf4196 Datasheet - Page 23

• Manufacturer Part Number: adf4196
• Description: Low Phase Noise, Fast Settling, 6 Ghz Pll Frequency Synthesizer
• Manufacturer: Analog Devices, Inc.

Data Sheet
Reference Spurs
Reference spurs are generally not a problem in fractional-N
synthesizers because the reference offset is far outside the loop
bandwidth. However, any reference feedthrough mechanism
that bypasses the loop can cause a problem. One such mechanism
is feedthrough of low levels of on-chip reference switching noise
out of the RF
spur levels as high as −90 dBc. These spurs can be suppressed
below −110 dBc by inserting sufficient reverse isolation, for
example, through an RF buffer between the VCO and RF
Also, take care in the printed circuit board (PCB) layout to ensure
that the VCO is well separated from the input reference to avoid
a possible feedthrough path on the board.
POWER-UP INITIALIZATION
After applying power to the
sequence is recommended, as described in Table 9.
The divider and timer settings used in the example in Table 9 are
for a DCS1800 Tx synthesizer with a 104 MHz REF
The
grammed channel frequency after Step 14.
Table 9. Power-Up Initialization Sequence A and
Initialization Sequence B
Step
1
2
Wait
10 ms
3
4
5A
5B
6
7
8
9
10
11
12
13
14
1
Sequence B includes Step 5B and omits Step 5A.
Initialization Sequence A includes Step 5A and omits Step 5B; Initialization
ADF4196
1
Register/
Bits
R5 [7:0]
R3 [15:0]
R7 [15:0]
R6 [15:0]
R6 [15:0]
R6 [15:0]
R4 [23:0]
R4 [23:0]
R4 [23:0]
R2 [15:0]
R1 [23:0]
R0 [23:0]
R3 [15:0]
R5 [7:0]
R0 [23:0]
IN±
powers up after Step 13 and locks to the pro-
pins back to the VCO, resulting in reference
Hex Code
0xFD
0x005B
0x0007
0x000E
0x900E
0x000E
0x004464
0x00446C
0x004394
0x00D2
0x520209
0x480140
0x007B
0x05
0x480140
ADF4196
Description
Set all power-down bits.
PFD polarity = 1, ground
CP
Allow time for loop filter
capacitors to discharge.
Clear test modes.
Initialize PLL modes, digital
lock detect on MUX
10 ns lock detect threshold,
digital lock detect on MUX
Add 16 PFD cycle delay after
LE before starting hop to next
frequency.
SW1/SW2 timer = 10.8 μs.
SW3 timer = 10.8 μs.
I
Phase = 26.
8/9 prescaler, doubler disabled,
R = 4, toggle FF on, MOD = 65.
INT = 144, FRAC = 40 for
1880 MHz output frequency.
PFD polarity = 1, release
CP
Clear all power-down bits.
INT = 144, FRAC = 40 for
1880 MHz output frequency.
CP
for the first time, a 14-2530
OUT+
OUT
timer = 8.6 μs.
+/CP
/CP
OUT−
OUT−
.
.
IN
frequency.
OUT
IN±
.
pins.
OUT
Rev. B | Page 23 of 28
.
Two initialization sequences are available for the ADF4196:
Initialization Sequence A and Initialization Sequence B. One or
the other must be selected. Initialization Sequence A consists of
Step 1 through Step 14 in Table 9, including Step 5A (but not
Step 5B). (For Initialization Sequence B, Step 5A is replaced by
Step 5B.) In Initialization Sequence A, the frequency hop starts
immediately after the rising edge of LE, whereas in Initialization
Sequence B, the
hop. Initialization Sequence B reduces the overshoot of a
frequency jump, but the start of a jump is delayed by 16 PFD
cycles. Figure 36 shows this phenomenon.
CHANGING THE FREQUENCY OF THE PLL AND THE
PHASE LOOKUP TABLE
After the
required to program a new output frequency. The N divider is
updated with the values of INT and FRAC on the next PFD cycle
following the LE edge that latches in the R0 word. However, the
settling time and spurious performance of the synthesizer can
be further optimized by modifying the R1 and R2 register settings
on a channel-by-channel basis. These settings are double buffered
by the write to R0. This means that, although the data is loaded
through the serial interface on the respective R1 and R2 write
cycles, the synthesizer is not updated with the new data until
the next write to Register R0.
Register R2 can be used to digitally adjust the phase of the VCO
output relative to the reference edge. The phase can be adjusted
over the full 360° range at RF with a resolution of 360°/MOD.
In most frequency synthesizer applications, the actual phase offset
of the VCO output with respect to the reference is unknown
and is irrelevant. In such applications, the phase adjustment
capability of R2 can, instead, be used to optimize the settling time
performance as described in the Phase Lookup Table section.
LE
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
Figure 36. Frequency Jumps for Initialization Sequence A and
ADF4196
INITIALIZATION SEQUENCE A
ADF4196
INITIALIZATION SEQUENCE B
is initialized, only a write to Register R0 is
Initialization Sequence B
waits 16 PFD cycles and then starts the
TIME (µs/DIV)
ADF4196