dac1628d1g25 NXP Semiconductors, dac1628d1g25 Datasheet - Page 109

• Manufacturer Part Number: dac1628d1g25
• Description: Dual 16-bit Dac Jesd204b Interface Up To 1.25 Gsps; X2, X4 And X8 Interpolating
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 133. HS_REF_EN register (address 00h) bit description
Default values are shown highlighted.
Table 134. HS_REF_POLY_TRIM register (address 01h) bit description
Default values are shown highlighted.
Table 135. HS_RX_CDR_DIV register (address 02h) bit description
Default values are shown highlighted.
Table 136. HS_RX_CDR_CP register(address 03h) bit description
Default values are shown highlighted.
Table 137. HS_RX_CDR_LOOP register(address 04h) bit description
Default values are shown highlighted.
DAC1628D1G25
Objective data sheet
Bit
2
1
0
Bit
5 to 0
Bit
7
6 to 5
4 to 0
Bit
7 to 4
3 to 0
Bit
7 to 5
4 to 2
1 to 0
Symbol
HS_RX_CDR_LOOP_RZ_TRACK[2:0]
HS_RX_CDR_LOOP_RZ_RUNIN[2:0]
HS_RX_CDR_LOOP_CAP[1:0]
Symbol
HS_REF_TUNE_EN
HS_REF_CAL_EN
HS_REF_EN
Symbol
HS_REF_POLY_TRIM[5:0]
Symbol
HS_RX_CDR_LOW_SPEED_EN
HS_RX_CDR_DIVM[1:0]
HS_RX_CDR_DIVN[4:0]
Symbol
HS_RX_CDR_CP_IUP[3:0]
HS_RX_CDR_CP_IDW[3:0]
10.17.8.2 Page x10 bit definition detailed description
The tables in this section contain detailed descriptions of the page x10 registers.
Access
R/W
R/W
R/W
Access
R/W
Access
R/W
R/W
All information provided in this document is subject to legal disclaimers.
R/W
R/W
R/W
Access
Rev. 1.1 — 10 October 2011
Value
0
1
0
1
0
1
Access
R/W
R/W
R/W
Value
-
Value
-
-
Dual 16-bit DAC: JESD204B interface; up to 1.25 Gsps
Value
0
1
-
-
Description
continuous calibration mode
calibration mode
hs_ref module
Value
-
-
-
hs_ref is not in continuous calibration mode
hs_ref is in continuous calibration mode
hs_ref is not in calibration mode
hs_ref in calibration mode (when hs_ref_tune_en is low)
disabled (power-down)
enabled (active)
Description
hs_ref poly trimming inputs (actually not used)
Description
sets charge pump up-current (~0.5 to ~ 8.0 A)
sets charge pump down-current (~0.5 to ~8.0 A)
Description
low speed mode
divm ratio used to divide refclk (predivider)
divn ratio used in CDR reference loop
disabled
enabled
Description
CDR loop resistance value in track mode
CDR loop resistance value in run-in mode
CDR loop capacitance value
DAC1628D1G25
© NXP B.V. 2011. All rights reserved.
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