dac1628d1g25 NXP Semiconductors, dac1628d1g25 Datasheet - Page 110

• Manufacturer Part Number: dac1628d1g25
• Description: Dual 16-bit Dac Jesd204b Interface Up To 1.25 Gsps; X2, X4 And X8 Interpolating
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 138. HS_RX_CDR_EN registers (address 05h to 06h) bit description
Default values are shown highlighted.
DAC1628D1G25
Objective data sheet
Address Register
05h
06h
HS_RX_CDR_EN_0 3
HS_RX_CDR_EN_1 7
Bit
2
1
0
6
5
4
3
2
Symbol
HS_RX_3_CDR_EN
HS_RX_2_CDR_EN
HS_RX_1_CDR_EN
HS_RX_0_CDR_EN
HS_RX_3_CDR_FACQ_EN
HS_RX_2_CDR_FACQ_EN
HS_RX_1_CDR_FACQ_EN
HS_RX_0_CDR_FACQ_EN
HS_RX_3_CDR_TRACK_
DATA_EN
HS_RX_2_CDR_TRACK_
DATA_EN
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 October 2011
Dual 16-bit DAC: JESD204B interface; up to 1.25 Gsps
Access Value
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DAC1628D1G25
Description
CDR of rx of lane 3 disabled
(power-down)
CDR of rx of lane 3 enabled
(active)
CDR of rx_ln2 disabled
(power-down)
CDR of rx_ln2 enabled (active)
CDR of rx_ln1 disabled
(power-down)
CDR of rx_ln1 enabled (active)
CDR of rx_ln0 disabled
(power-down)
CDR of rx_ln0 enabled (active)
frequency acquisition mode
data tracking mode
CDR_ln3 frequency acquisition
mode disabled
CDR_ln3 frequency acquisition
mode enabled
CDR_ln2 frequency acquisition
mode disabled
CDR_ln2 frequency acquisition
mode enabled
CDR_ln1 frequency acquisition
mode disabled
CDR_ln1 frequency acquisition
mode enabled
CDR_ln0 frequency acquisition
mode disabled
CDR_ln0 frequency acquisition
mode enabled
CDR_ln3 in pfd mode
(reference loop)
CDR_ln3 in data tracking mode
(normal mode)
CDR_ln2 in pfd mode
(reference loop)
CDR_ln2 in data tracking mode
(normal mode)
© NXP B.V. 2011. All rights reserved.
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