dac1628d1g25 NXP Semiconductors, dac1628d1g25 Datasheet - Page 83
dac1628d1g25
Manufacturer Part Number
dac1628d1g25
Description
Dual 16-bit Dac Jesd204b Interface Up To 1.25 Gsps; X2, X4 And X8 Interpolating
Manufacturer
NXP Semiconductors
Datasheet
1.DAC1628D1G25.pdf
(133 pages)
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Table 100. INTR_MISC_ENA register (address 0Fh) bit description
Default settings are shown highlighted.
Table 101. LSB/MSB of flag_counter lane registers (address 10h to 17h) bit description
Default settings are shown highlighted.
Table 102. LSB/MSB BER measurement registers (address 18h to 19h) bit description
Default settings are shown highlighted.
Table 103. INTR_ENA register (address 1Ah) bit description
DAC1628D1G25
Objective data sheet
Bit
2
1
0
Address Register
10h
11h
12h
13h
14h
15h
16h
17h
Address
18h
19h
Bit
7
6
5
Symbol
INTR_EN_BUF_ERR_LN2
INTR_EN_BUF_ERR_LN1
INTR_EN_BUF_ERR_LN0
Symbol
INTR_EN_NIT
INTR_EN_DISP
INTR_EN_KOUT
FLAG_CNT_LSB_LN0 7 to 0
FLAG_CNT_MSB_LN0 7 to 0
FLAG_CNT_LSB_LN1 7 to 0
FLAG_CNT_MSB_LN1 7 to 0
FLAG_CNT_LSB_LN2 7 to 0
FLAG_CNT_MSB_LN2 7 to 0
FLAG_CNT_LSB_LN3 7 to 0
FLAG_CNT_MSB_LN3 7 to 0
Register
BER_LVL_LSB
BER_LVL_MSB
Bit
7 to 0
7 to 0
Bit
All information provided in this document is subject to legal disclaimers.
Symbol
FLAG_CNT_LN0[7:0]
FLAG_CNT_LN0[15:8] R
FLAG_CNT_LN1[7:0]
FLAG_CNT_LN1[15:8] R
FLAG_CNT_LN2[7:0]
FLAG_CNT_LN2[15:8] R
FLAG_CNT_LN3[7:0]
FLAG_CNT_LN3[15:8] R
Symbol
BER_LVL[7:0]
BER_LVL[15:8]
Rev. 1.1 — 10 October 2011
Access
R/W
R/W
R/W
Access
R/W
R/W
R/W
Dual 16-bit DAC: JESD204B interface; up to 1.25 Gsps
Value
0
1
0
1
0
1
Value
0
1
0
1
0
1
Access
R/W
R/W
Access Value
R
R
R
R
…continued
Description
no action
generate interrupt if ILA_BUF_ERR_LN2 = 1
no action
generate interrupt if ILA_BUF_ERR_LN1 = 1
no action
generate interrupt if ILA_BUF_ERR_LN0 = 1
Description
not-in-table interrupt
K-character interrupt
disparity-error interrupt
no action
nit_error impacts global interrupt as per
INTR_MODE configuration (bit 1E)
no action
disparity-error in ln<x> affects i_ln<x>
no action
detection k-control character in ln<x> affects
i_ln<x>
Value
00h
00h
-
-
-
-
-
-
-
-
Description
LSBs level used for simple (DC)
BER measurement
MSBs level used for simple (DC)
BER measurement
DAC1628D1G25
Description
LSBs of flag counter lane 0
MSBs of flag_counter lane 0
LSBs of flag_counter lane 1
MSBs of flag_counter lane 1
LSBs of flag_counter lane 2
MSBs of flag_counter lane 2
LSBs of flag_counter lane 3
MSBs of flag_counter lane 3
© NXP B.V. 2011. All rights reserved.
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