dac1628d1g25 NXP Semiconductors, dac1628d1g25 Datasheet - Page 76

• Manufacturer Part Number: dac1628d1g25
• Description: Dual 16-bit Dac Jesd204b Interface Up To 1.25 Gsps; X2, X4 And X8 Interpolating
• Manufacturer: NXP Semiconductors

NXP Semiconductors
DAC1628D1G25
Objective data sheet
Fig 27. Page x04: RX digital lane processing monitoring
PAGE x04: RX DLP MONITORING
ILA_MON_LN0
ILA_BUFF_ERR_LN0
ILA_MON_LN1
ILA_BUFF_ERR_LN1
ILA_MON_LN2
ILA_BUFF_ERR_LN2
ILA_MON_LN3
ILA_BUFF_ERR_LN3
ILA MONITORING
ILA MON LANE 0
ILA MON LANE 1
ILA MON LANE 2
ILA MON LANE 3
10.17.5 Page x04: RX digital lane processing monitoring
RST_K28_FLAGS_LN0
RST_K28_FLAGS_LN1
RST_K28_FLAGS_LN2
RST_K28_FLAGS_LN3
DEC_NIT_ERR_LN0
DEC_DISP_ERR_LN0
DEC_KOUT_LN0
DEC_KOUT_UNEXP_LN0
DEC_NIT_ERR_LN1
DEC_DISP_ERR_LN1
DEC_KOUT_LN1
DEC_KOUT_UNEXP_LN1
DEC_NIT_ERR_LN2
DEC_DISP_ERR_LN2
DEC_KOUT_LN2
DEC_KOUT_UNEXP_LN2
DEC_NIT_ERR_LN3
DEC_DISP_ERR_LN3
DEC_KOUT_LN3
DEC_KOUT_UNEXP_LN3
This page enables the monitoring of the digital lane processing, ensuring the data is
decoded correctly. The validity of the link can also be tested by using simple Bit Error Rate
testing and be monitored through various available flags and counters registers.
10B/8B DECODER MONITORING
DECODER LANE 0
DECODER LANE 1
DECODER LANE 2
DECODER LANE 3
RESET
RST_KOUT_UNEXP_FLAGS
RST_KOUT_FLAGS
RST_DSIP_ERR_FLAGS
RST_NIT_ERR_FLAGS
K28_7_LN0
K28_5_LN0
K28_4_LN0
K28_3_LN0
K28_0_LN0
K28_7_LN1
K28_5_LN1
K28_4_LN1
K28_3_LN1
K28_0_LN1
K28_7_LN2
K28_5_LN2
K28_4_LN2
K28_3_LN2
K28_0_LN2
K28_7_LN3
K28_5_LN3
K28_4_LN3
K28_3_LN3
K28_0_LN3
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 October 2011
RST_CFC_LN0
SEL_CFC_LN0
ber_ln0, cm_0, nit_err_ln0, disp_err_ln0,
kout_ln0, kout_unexp_ln0, k28_7_ln0,
k28_5_ln0, k28_3_ln0, k28_0_ln0,
RST_CFC_LN1
SEL_CFC_LN1
ber_ln1, cm_1, nit_err_ln1, disp_err_ln1,
kout_ln1, kout_unexp_ln1, k28_7_ln1,
k28_5_ln1, k28_3_ln1, k28_0_ln1,
RST_CFC_LN2
SEL_CFC_LN2
ber_ln2, cm_2, nit_err_ln2, disp_err_ln2,
kout_ln2, kout_unexp_ln2, k28_7_ln2,
k28_5_ln2, k28_3_ln2, k28_0_ln2,
RST_CFC_LN3
SEL_CFC_LN3
ber_ln3, cm_3, nit_err_ln3, disp_err_ln3,
kout_ln3, kout_unexp_ln3, k28_7_ln3,
k28_5_ln3, k28_3_ln3, k28_0_ln3,
FLAG COUNTER LANE 0
FLAG COUNTER LANE 1
FLAG COUNTER LANE 2
FLAG COUNTER LANE 3
Dual 16-bit DAC: JESD204B interface; up to 1.25 Gsps
FLAG COUNTERS
FLAG_CNT_LN0
FLAG_CNT_LN1
FLAG_CNT_LN2
FLAG_CNT_LN3
BER_LVL
(I/Q DC levels used for BER test are specified on page x0A)
INTR_CLR
INTR_MODE:
intr depends on ln0
intr depends on ln1
intr depends on ln2
intr depends on ln3
intr depends on ln0 or ln2
intr depends on ln0 or ln1 or ln2 or ln3
no interrupt
DAC1628D1G25
DLP INTERRUPT
BER_MODE
BER
© NXP B.V. 2011. All rights reserved.
INTR_EN_NIT
INTR_EN_DISP
INTR_EN_KOUT
INTR_EN_KOUT_UNEXP
INTR_EN_K28_7
INTR_EN_K28_5
INTR_EN_K28_3
INTR_EN_MISC
aaa-000286
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