dac1628d1g25 NXP Semiconductors, dac1628d1g25 Datasheet - Page 70

• Manufacturer Part Number: dac1628d1g25
• Description: Dual 16-bit Dac Jesd204b Interface Up To 1.25 Gsps; X2, X4 And X8 Interpolating
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 77.
Default settings are shown highlighted.
Table 78.
Default settings are shown highlighted.
DAC1628D1G25
Objective data sheet
Address Register
09h
0Ah
Bit
7 to 6
5 to 4
3 to 2
1 to 0
Symbol
SEL_KOUT_ UNEXP_LN32[1:0]
SEL_KOUT_ UNEXP_LN10[1:0]
SEL_NIT_ERR_ LN32[1:0]
SEL_NIT_ERR_ LN10[1:0]
MAN_ALIGN_LN_1_0
MAN_ALIGN_LN_3_2
Manual alignment registers (address 09h to 0Ah) bit description
FA_ERR_HANDLING register (address 0Bh) bit description
Bit
7 to 4
3 to 0
7 to 4
3 to 0
All information provided in this document is subject to legal disclaimers.
Symbol
MAN_ALIGN_LN1[3:0] R/W
MAN_ALIGN_LN0[3:0]
MAN_ALIGN_LN3[3:0] R/W
MAN_ALIGN_LN2[3:0]
Rev. 1.1 — 10 October 2011
Access
R/W
R/W
R/W
R/W
Dual 16-bit DAC: JESD204B interface; up to 1.25 Gsps
Value
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
Access Value
Description
lane 3/lane 2 unexpected /K/ error handling
lane 1/lane 0 unexpected /K/ error handling
lane 3/lane 2 nit-error handling
lane 1/lane 0 nit-error handling
unexpected /K/ in lane 0 and lane 1 error_handling
unexpected /K/ in lane 0 error_handling
unexpected /K/ in lane 1 error_handling
not-in-table errors in lane 2 error_handling
not-in-table errors in lane 3 error_handling
not-in-table errors in lane 0 error_handling
not-in-table errors in lane 1 error_handling
unexpected /K/ in lane 2 or lane 3
error_handling
unexpected /K/ in lane 2 and lane 3 error_handling
unexpected /K/ in lane 2 error_handling
unexpected /K/ in lane 3 error_handling
unexpected /K/ in lane 0 or lane 1
error_handling
nit-errors in lane 2 or lane 3 error_handling
not-in-table errors lane 2 and lane 3
error_handling
nit-errors in lane 0 or lane 1 error_handling
not-in-table errors lane 0 and lane 1
error_handling
0h
0h
0h
0h
DAC1628D1G25
Description
indicates alignment data-delay for
lane 1 [1..15]
indicates alignment data-delay for
lane 0 [1..15]
indicates alignment data-delay for
lane 3 [1..15]
indicates alignment data-delay for
lane 2 [1..15]
© NXP B.V. 2011. All rights reserved.
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