ep3c120f780c8nes Altera Corporation, ep3c120f780c8nes Datasheet - Page 127

• Manufacturer Part Number: ep3c120f780c8nes
• Description: Cyclone Iii Device Family
• Manufacturer: Altera Corporation

Altera Corporation-Preliminary
March 2007
You must assert the areset signal every time the PLL loses lock to
guarantee the correct phase relationship between the PLL input clock and
output clocks. You must include the areset signal in designs if one of the
following conditions is true:
■
■
1
locked
The locked output indicates that the PLL has locked onto the reference
clock and the PLL clock outputs are operating at the desired phase and
frequency set in the Quartus II Megawizard. Without any additional
circuitry, the lock signal toggles as the PLL begins the locking process.
The lock detection block provides a signal to core-logic that gives an
indication if the feedback clock has locked onto the reference clock both
in phase and frequency.
1
Clock Switchover
The clock switchover feature allows the PLL to switch between two
reference input clocks. Use this feature for clock redundancy or for a dual
clock domain application such as in a system that turns on the redundant
clock if the previous clock stops running. The design can perform clock
switchover automatically, when the clock is no longer toggling, or based
on a user control signal, clkswitch.
PLL reconfiguration or clock switchover enabled in the design
Phase relationships between the PLL input clock and output clocks
need to be maintained after a loss of lock condition
If the input clock to the PLL is toggling or unstable upon power
up, assert the areset signal after the input clock is stable and
within specifications.
Altera recommends that you use the areset and locked
signals in your designs to control and observe the status of your
PLL.
Cyclone III Device Handbook, Volume 1
Hardware Features
6–27